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| author |   Maciej W. Rozycki <macro@linux-mips.org> | 2015-04-03 23:27:38 +0100 |
|---|---|---|
| committer |   Ralf Baechle <ralf@linux-mips.org> | 2015-04-08 01:10:31 +0200 |
| commit | f1f3b7ebac08161761c352fd070cfa07b7b94c54 (patch) | |
| tree | bd02705eb60a81da45d40827dcfec70dd31ab622 /arch/mips/math-emu | |
| parent | MIPS: math-emu: Implement the FCCR, FEXR and FENR registers (diff) | |
| download | linux-dev-f1f3b7ebac08161761c352fd070cfa07b7b94c54.tar.xz linux-dev-f1f3b7ebac08161761c352fd070cfa07b7b94c54.zip | |
MIPS: math-emu: Define IEEE 754-2008 feature control bits
Define IEEE 754-2008 feature control bits: FIR.HAS2008, FCSR.ABS2008 and
FCSR.NAN2008, and update the `_ieee754_csr' structure accordingly.
For completeness define FIR.UFRP too.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9709/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/math-emu')
| -rw-r--r-- | arch/mips/math-emu/cp1emu.c | 5 | ||||
| -rw-r--r-- | arch/mips/math-emu/ieee754.h | 12 |
2 files changed, 10 insertions, 7 deletions
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index 8034ee4c3341..3a90170a6277 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -919,8 +919,9 @@ static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx, pr_debug("%p gpr[%d]->csr=%08x\n", (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); - /* Don't write reserved bits. */ - fcr31 = value & ~FPU_CSR_RSVD; + /* Don't write unsupported bits. */ + fcr31 = value & + ~(FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008); break; case FPCREG_FENR: diff --git a/arch/mips/math-emu/ieee754.h b/arch/mips/math-emu/ieee754.h index 918334465212..a5ca108ce467 100644 --- a/arch/mips/math-emu/ieee754.h +++ b/arch/mips/math-emu/ieee754.h @@ -130,15 +130,17 @@ enum { * The control status register */ struct _ieee754_csr { - __BITFIELD_FIELD(unsigned pad0:7, - __BITFIELD_FIELD(unsigned nod:1, /* set 1 for no denormalised numbers */ - __BITFIELD_FIELD(unsigned c:1, /* condition */ - __BITFIELD_FIELD(unsigned pad1:5, + __BITFIELD_FIELD(unsigned fcc:7, /* condition[7:1] */ + __BITFIELD_FIELD(unsigned nod:1, /* set 1 for no denormals */ + __BITFIELD_FIELD(unsigned c:1, /* condition[0] */ + __BITFIELD_FIELD(unsigned pad0:3, + __BITFIELD_FIELD(unsigned abs2008:1, /* IEEE 754-2008 ABS/NEG.fmt */ + __BITFIELD_FIELD(unsigned nan2008:1, /* IEEE 754-2008 NaN mode */ __BITFIELD_FIELD(unsigned cx:6, /* exceptions this operation */ __BITFIELD_FIELD(unsigned mx:5, /* exception enable mask */ __BITFIELD_FIELD(unsigned sx:5, /* exceptions total */ __BITFIELD_FIELD(unsigned rm:2, /* current rounding mode */ - ;)))))))) + ;)))))))))) }; #define ieee754_csr (*(struct _ieee754_csr *)(¤t->thread.fpu.fcr31)) |