diff options
| author |   Chris Dearman <chris@mips.com> | 2007-05-08 14:05:39 +0100 |
|---|---|---|
| committer |   Ralf Baechle <ralf@linux-mips.org> | 2007-05-11 14:28:31 +0100 |
| commit | d725cf3818b12a17d78b87a2de19e8eec17126ae (patch) | |
| tree | 9d200020488b886201771bd6516c63ef43397baa /arch/mips/mips-boards | |
| parent | [MIPS] Define and use vi_handler_t for vectored interrupt handlers. (diff) | |
| download | linux-dev-d725cf3818b12a17d78b87a2de19e8eec17126ae.tar.xz linux-dev-d725cf3818b12a17d78b87a2de19e8eec17126ae.zip | |
[MIPS] MT: Reenable EIC support and add support for SOCit SC.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mips-boards')
| -rw-r--r-- | arch/mips/mips-boards/malta/malta_int.c | 21 |
1 files changed, 13 insertions, 8 deletions
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c index 83d76025d61d..1cd830e3d933 100644 --- a/arch/mips/mips-boards/malta/malta_int.c +++ b/arch/mips/mips-boards/malta/malta_int.c @@ -311,16 +311,21 @@ void __init arch_init_irq(void) if (!cpu_has_veic) mips_cpu_irq_init(); - switch(mips_revision_corid) { - case MIPS_REVISION_CORID_CORE_MSC: - case MIPS_REVISION_CORID_CORE_FPGA2: - case MIPS_REVISION_CORID_CORE_FPGA3: - case MIPS_REVISION_CORID_CORE_24K: - case MIPS_REVISION_CORID_CORE_EMUL_MSC: + switch(mips_revision_sconid) { + case MIPS_REVISION_SCON_SOCIT: + case MIPS_REVISION_SCON_ROCIT: + if (cpu_has_veic) + init_msc_irqs (MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); + else + init_msc_irqs (MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); + break; + + case MIPS_REVISION_SCON_SOCITSC: + case MIPS_REVISION_SCON_SOCITSCP: if (cpu_has_veic) - init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); + init_msc_irqs (MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); else - init_msc_irqs (MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); + init_msc_irqs (MIPS_SOCITSC_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); } if (cpu_has_veic) { |