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authorChristoph Hellwig <hch@lst.de>2018-07-27 19:26:06 +0200
committerPaul Burton <paul.burton@mips.com>2018-07-27 15:19:59 -0700
commita999933db9ed44f8501e0241f7f1fbdf36554396 (patch)
tree582181edf96f6389672c90b94654dd6acbaa9aaf /arch/mips/mm/Makefile
parentMIPS: WARN_ON invalid DMA cache maintenance, not BUG_ON (diff)
downloadlinux-dev-a999933db9ed44f8501e0241f7f1fbdf36554396.tar.xz
linux-dev-a999933db9ed44f8501e0241f7f1fbdf36554396.zip
MIPS: remove mips_swiotlb_ops
mips_swiotlb_ops differs from the generic swiotlb_dma_ops only in that it contains a mb() barrier after each operations that maps or syncs dma memory to the device. The dma operations are defined to not be memory barriers, but instead the write* operations to kick the DMA off are supposed to contain them. For mips this handled by war_io_reorder_wmb(), which evaluates to the stronger wmb() instead of the pure compiler barrier barrier() for just those platforms that use swiotlb, so I think we are covered properly. [paul.burton@mips.com: - Include linux/swiotlb.h to fix build failures for configs with CONFIG_SWIOTLB=y.] Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20038/ Cc: David Daney <ddaney@caviumnetworks.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: linux-mips@linux-mips.org Cc: iommu@lists.linux-foundation.org Cc: linux-kernel@vger.kernel.org
Diffstat (limited to 'arch/mips/mm/Makefile')
-rw-r--r--arch/mips/mm/Makefile1
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index 6922f393af19..3e5bb203c95a 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -18,7 +18,6 @@ obj-$(CONFIG_64BIT) += pgtable-64.o
obj-$(CONFIG_HIGHMEM) += highmem.o
obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
obj-$(CONFIG_DMA_NONCOHERENT) += dma-noncoherent.o
-obj-$(CONFIG_SWIOTLB) += dma-swiotlb.o
obj-$(CONFIG_CPU_R4K_CACHE_TLB) += c-r4k.o cex-gen.o tlb-r4k.o
obj-$(CONFIG_CPU_R3000) += c-r3k.o tlb-r3k.o