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| author |   Markos Chandras <markos.chandras@imgtec.com> | 2014-12-02 15:30:19 +0000 |
|---|---|---|
| committer | Markos Chandras <markos.chandras@imgtec.com> | 2015-02-17 15:37:31 +0000 |
| commit | 4ee486274ec1e63f056c991e2523c32780670d08 (patch) | |
| tree | 2304dbbb0b303b67d5622cddb95abc62331a1677 /arch/mips/mm/sc-mips.c | |
| parent | MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazard for the EHB instruction (diff) | |
| download | linux-dev-4ee486274ec1e63f056c991e2523c32780670d08.tar.xz linux-dev-4ee486274ec1e63f056c991e2523c32780670d08.zip | |
MIPS: mm: c-r4k: Set the correct ISA level
The local_r4k_flush_cache_sigtramp function uses the 'cache'
instruction inside an asm block. However, MIPS R6 changed the
opcode for the cache instruction and as a result of which we
need to set the correct ISA level.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Diffstat (limited to 'arch/mips/mm/sc-mips.c')
0 files changed, 0 insertions, 0 deletions