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author | Russell King <rmk+kernel@arm.linux.org.uk> | 2015-07-07 12:35:33 +0100 |
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committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2015-07-07 12:35:33 +0100 |
commit | 06be5eefe1192eb8ce8d07497f67595b6bfe9741 (patch) | |
tree | 80f1987d4970f8079681f8be0c135cafc8d6329a /arch/mips/pci/pci-ar71xx.c | |
parent | ARM: fix lockdep unannotated irqs-off warning (diff) | |
parent | ARM: avoid unwanted GCC memset()/memcpy() optimisations for IO variants (diff) | |
download | linux-dev-06be5eefe1192eb8ce8d07497f67595b6bfe9741.tar.xz linux-dev-06be5eefe1192eb8ce8d07497f67595b6bfe9741.zip |
Merge branches 'fixes' and 'ioremap' into for-linus
Diffstat (limited to 'arch/mips/pci/pci-ar71xx.c')
-rw-r--r-- | arch/mips/pci/pci-ar71xx.c | 14 |
1 files changed, 2 insertions, 12 deletions
diff --git a/arch/mips/pci/pci-ar71xx.c b/arch/mips/pci/pci-ar71xx.c index 9e62ad31d4b5..283157f8dc64 100644 --- a/arch/mips/pci/pci-ar71xx.c +++ b/arch/mips/pci/pci-ar71xx.c @@ -232,7 +232,7 @@ static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc) void __iomem *base = ath79_reset_base; u32 pending; - apc = irq_get_handler_data(irq); + apc = irq_desc_get_handler_data(desc); pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) & __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); @@ -318,23 +318,13 @@ static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc) static void ar71xx_pci_reset(void) { - void __iomem *ddr_base = ath79_ddr_base; - ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE); mdelay(100); ath79_device_reset_clear(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE); mdelay(100); - __raw_writel(AR71XX_PCI_WIN0_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN0); - __raw_writel(AR71XX_PCI_WIN1_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN1); - __raw_writel(AR71XX_PCI_WIN2_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN2); - __raw_writel(AR71XX_PCI_WIN3_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN3); - __raw_writel(AR71XX_PCI_WIN4_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN4); - __raw_writel(AR71XX_PCI_WIN5_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN5); - __raw_writel(AR71XX_PCI_WIN6_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN6); - __raw_writel(AR71XX_PCI_WIN7_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN7); - + ath79_ddr_set_pci_windows(); mdelay(100); } |