diff options
| author |   Jayachandran C <jchandra@broadcom.com> | 2013-12-21 16:52:13 +0530 |
|---|---|---|
| committer |   Ralf Baechle <ralf@linux-mips.org> | 2014-01-24 22:39:46 +0100 |
| commit | c24a8a7a99885d5b986f38f6631f69e7794a3e5e (patch) | |
| tree | a0d6702fc1c45cba157a5734215c509fa4b216c6 /arch/mips/pci/pci-xlp.c | |
| parent | MIPS: malta: Incorporate PIIX4 ACPI I/O region in PCI controller resources (diff) | |
| download | linux-dev-c24a8a7a99885d5b986f38f6631f69e7794a3e5e.tar.xz linux-dev-c24a8a7a99885d5b986f38f6631f69e7794a3e5e.zip | |
MIPS: Netlogic: Add MSI support for XLP
Add MSI chip and MSIX chip definitions.
For MSI, we map the link interrupt to a MSI link IRQ which will
do a second level of dispatch based on the MSI status register.
The MSI chip definitions use the MSI enable register to enable
and disable the MSI irqs.
For MSI-X, we split the 32 available MSI-X vectors across the
four PCIe links (8 each). These PIC interrupts generate an IRQ
per link which uses a second level dispatch as well.
The MSI-X chip definition uses the standard functions to enable
and disable interrupts.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6270/
Diffstat (limited to 'arch/mips/pci/pci-xlp.c')
| -rw-r--r-- | arch/mips/pci/pci-xlp.c | 15 |
1 files changed, 6 insertions, 9 deletions
diff --git a/arch/mips/pci/pci-xlp.c b/arch/mips/pci/pci-xlp.c index 653d2db9e0c5..222d804e77d1 100644 --- a/arch/mips/pci/pci-xlp.c +++ b/arch/mips/pci/pci-xlp.c @@ -47,6 +47,7 @@ #include <asm/netlogic/interrupt.h> #include <asm/netlogic/haldefs.h> #include <asm/netlogic/common.h> +#include <asm/netlogic/mips-extns.h> #include <asm/netlogic/xlp-hal/iomap.h> #include <asm/netlogic/xlp-hal/pic.h> @@ -162,7 +163,7 @@ struct pci_controller nlm_pci_controller = { .io_offset = 0x00000000UL, }; -static struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev) +struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev) { struct pci_bus *bus, *p; @@ -174,11 +175,6 @@ static struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev) return p ? bus->self : NULL; } -static inline int nlm_pci_link_to_irq(int link) -{ - return PIC_PCIE_LINK_0_IRQ + link; -} - int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { struct pci_dev *lnkdev; @@ -193,7 +189,7 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return 0; lnkfunc = PCI_FUNC(lnkdev->devfn); lnkslot = PCI_SLOT(lnkdev->devfn); - return nlm_irq_to_xirq(lnkslot / 8, nlm_pci_link_to_irq(lnkfunc)); + return nlm_irq_to_xirq(lnkslot / 8, PIC_PCIE_LINK_LEGACY_IRQ(lnkfunc)); } /* Do platform specific device initialization at pci_enable_device() time */ @@ -257,16 +253,17 @@ static int __init pcibios_init(void) if (!nodep->coremask) continue; /* node does not exist */ - for (link = 0; link < 4; link++) { + for (link = 0; link < PCIE_NLINKS; link++) { pciebase = nlm_get_pcie_base(n, link); if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff) continue; xlp_config_pci_bswap(n, link); + xlp_init_node_msi_irqs(n, link); /* put in intpin and irq - u-boot does not */ reg = nlm_read_pci_reg(pciebase, 0xf); reg &= ~0x1fu; - reg |= (1 << 8) | nlm_pci_link_to_irq(link); + reg |= (1 << 8) | PIC_PCIE_LINK_LEGACY_IRQ(link); nlm_write_pci_reg(pciebase, 0xf, reg); pr_info("XLP PCIe: Link %d-%d initialized.\n", n, link); } |