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| author |   Paul Burton <paul.burton@mips.com> | 2019-10-01 21:53:44 +0000 |
|---|---|---|
| committer | Paul Burton <paul.burton@mips.com> | 2019-10-07 09:43:13 -0700 |
| commit | e4acfbc18fc9e0d75ad15a652864b3971892e423 (patch) | |
| tree | 6b6024d6dbbedd60e17018adc13e7bbeae0127e4 /arch/mips/sgi-ip27/ip27-memory.c | |
| parent | MIPS: genex: Don't reload address unnecessarily (diff) | |
| download | linux-dev-e4acfbc18fc9e0d75ad15a652864b3971892e423.tar.xz linux-dev-e4acfbc18fc9e0d75ad15a652864b3971892e423.zip | |
MIPS: Check Loongson3 LL/SC errata workaround correctness
When Loongson3 LL/SC errata workarounds are enabled (ie.
CONFIG_CPU_LOONGSON3_WORKAROUNDS=y) run a tool to scan through the
compiled kernel & ensure that the workaround is applied correctly. That
is, ensure that:
- Every LL or LLD instruction is preceded by a sync instruction.
- Any branches from within an LL/SC loop to outside of that loop
target a sync instruction.
Reasoning for these conditions can be found by reading the comment above
the definition of __SYNC_loongson3_war in arch/mips/include/asm/sync.h.
This tool will help ensure that we don't inadvertently introduce code
paths that miss the required workarounds.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: linux-kernel@vger.kernel.org
Diffstat (limited to 'arch/mips/sgi-ip27/ip27-memory.c')
0 files changed, 0 insertions, 0 deletions