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| author |   James Morris <jmorris@namei.org> | 2009-05-08 17:56:47 +1000 |
|---|---|---|
| committer | James Morris <jmorris@namei.org> | 2009-05-08 17:56:47 +1000 |
| commit | d254117099d711f215e62427f55dfb8ebd5ad011 (patch) | |
| tree | 0848ff8dd74314fec14a86497f8d288c86ba7c65 /arch/mips/sni | |
| parent | integrity: remove __setup auditing msgs (diff) | |
| parent | NOMMU: Don't check vm_region::vm_start is page aligned in add_nommu_region() (diff) | |
| download | linux-dev-d254117099d711f215e62427f55dfb8ebd5ad011.tar.xz linux-dev-d254117099d711f215e62427f55dfb8ebd5ad011.zip | |
Merge branch 'master' into next
Diffstat (limited to 'arch/mips/sni')
| -rw-r--r-- | arch/mips/sni/a20r.c | 2 | ||||
| -rw-r--r-- | arch/mips/sni/pcimt.c | 2 | ||||
| -rw-r--r-- | arch/mips/sni/pcit.c | 4 | ||||
| -rw-r--r-- | arch/mips/sni/rm200.c | 5 |
4 files changed, 7 insertions, 6 deletions
diff --git a/arch/mips/sni/a20r.c b/arch/mips/sni/a20r.c index 3f8cf5eb2f06..7dd76fb3b645 100644 --- a/arch/mips/sni/a20r.c +++ b/arch/mips/sni/a20r.c @@ -219,7 +219,7 @@ void __init sni_a20r_irq_init(void) int i; for (i = SNI_A20R_IRQ_BASE + 2 ; i < SNI_A20R_IRQ_BASE + 8; i++) - set_irq_chip(i, &a20r_irq_type); + set_irq_chip_and_handler(i, &a20r_irq_type, handle_level_irq); sni_hwint = a20r_hwint; change_c0_status(ST0_IM, IE_IRQ0); setup_irq(SNI_A20R_IRQ_BASE + 3, &sni_isa_irq); diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c index 834650f371e0..74e6c67982fb 100644 --- a/arch/mips/sni/pcimt.c +++ b/arch/mips/sni/pcimt.c @@ -304,7 +304,7 @@ void __init sni_pcimt_irq_init(void) mips_cpu_irq_init(); /* Actually we've got more interrupts to handle ... */ for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_SCSI; i++) - set_irq_chip(i, &pcimt_irq_type); + set_irq_chip_and_handler(i, &pcimt_irq_type, handle_level_irq); sni_hwint = sni_pcimt_hwint; change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ3); } diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c index e5f12cf96e8e..071a9573ac7f 100644 --- a/arch/mips/sni/pcit.c +++ b/arch/mips/sni/pcit.c @@ -246,7 +246,7 @@ void __init sni_pcit_irq_init(void) mips_cpu_irq_init(); for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++) - set_irq_chip(i, &pcit_irq_type); + set_irq_chip_and_handler(i, &pcit_irq_type, handle_level_irq); *(volatile u32 *)SNI_PCIT_INT_REG = 0; sni_hwint = sni_pcit_hwint; change_c0_status(ST0_IM, IE_IRQ1); @@ -259,7 +259,7 @@ void __init sni_pcit_cplus_irq_init(void) mips_cpu_irq_init(); for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++) - set_irq_chip(i, &pcit_irq_type); + set_irq_chip_and_handler(i, &pcit_irq_type, handle_level_irq); *(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000; sni_hwint = sni_pcit_hwint_cplus; change_c0_status(ST0_IM, IE_IRQ0); diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c index 5310aa75afa4..5e687819cbc2 100644 --- a/arch/mips/sni/rm200.c +++ b/arch/mips/sni/rm200.c @@ -359,7 +359,8 @@ void sni_rm200_init_8259A(void) * IRQ2 is cascade interrupt to second interrupt controller */ static struct irqaction sni_rm200_irq2 = { - no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL + .handler = no_action, + .name = "cascade", }; static struct resource sni_rm200_pic1_resource = { @@ -487,7 +488,7 @@ void __init sni_rm200_irq_init(void) mips_cpu_irq_init(); /* Actually we've got more interrupts to handle ... */ for (i = SNI_RM200_INT_START; i <= SNI_RM200_INT_END; i++) - set_irq_chip(i, &rm200_irq_type); + set_irq_chip_and_handler(i, &rm200_irq_type, handle_level_irq); sni_hwint = sni_rm200_hwint; change_c0_status(ST0_IM, IE_IRQ0); setup_irq(SNI_RM200_INT_START + 0, &sni_rm200_i8259A_irq); |