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| author |   Atsushi Nemoto <anemo@mba.ocn.ne.jp> | 2008-08-19 22:55:09 +0900 |
|---|---|---|
| committer |   Ralf Baechle <ralf@linux-mips.org> | 2008-10-11 16:18:42 +0100 |
| commit | d10e025f0e4ba4b96d7b5786d232ac5b0b232b11 (patch) | |
| tree | a417a55071b4b7edc22b7c5bb1a2352e7b5986d9 /arch/mips/txx9/generic/setup_tx4927.c | |
| parent | MIPS: TXx9: Early command-line preprocessing (diff) | |
| download | linux-dev-d10e025f0e4ba4b96d7b5786d232ac5b0b232b11.tar.xz linux-dev-d10e025f0e4ba4b96d7b5786d232ac5b0b232b11.zip | |
MIPS: TXx9: Cache fixup
TX39/TX49 can enable/disable I/D cache at runtime. Add kernel options
to control them. This is useful to debug some cache-related issues,
such as aliasing or I/D coherency. Also enable CWF bit for TX49 SoCs.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/txx9/generic/setup_tx4927.c')
| -rw-r--r-- | arch/mips/txx9/generic/setup_tx4927.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/txx9/generic/setup_tx4927.c b/arch/mips/txx9/generic/setup_tx4927.c index f80d4b7a694d..e679c79a4b0f 100644 --- a/arch/mips/txx9/generic/setup_tx4927.c +++ b/arch/mips/txx9/generic/setup_tx4927.c @@ -44,6 +44,7 @@ void __init tx4927_setup(void) txx9_reg_res_init(TX4927_REV_PCODE(), TX4927_REG_BASE, TX4927_REG_SIZE); + set_c0_config(TX49_CONF_CWFON); /* SDRAMC,EBUSC are configured by PROM */ for (i = 0; i < 8; i++) { |