diff options
| author |   Paul Cercueil <paul@crapouillou.net> | 2018-03-28 17:38:12 +0200 |
|---|---|---|
| committer |   James Hogan <jhogan@kernel.org> | 2018-05-14 23:54:25 +0100 |
| commit | c60128ce97674fd05adb8b5ae79eb6745a03192e (patch) | |
| tree | 783beace1c1def02fc96d795e88c6e9c470c1398 /arch/mips | |
| parent | MIPS: c-r4k: Fix data corruption related to cache coherence (diff) | |
| download | linux-dev-c60128ce97674fd05adb8b5ae79eb6745a03192e.tar.xz linux-dev-c60128ce97674fd05adb8b5ae79eb6745a03192e.zip | |
MIPS: Fix build with DEBUG_ZBOOT and MACH_JZ4770
The debug definitions were missing for MACH_JZ4770, resulting in a build
failure when DEBUG_ZBOOT was set.
Since the UART addresses are the same across all Ingenic SoCs, we just
use a #ifdef CONFIG_MACH_INGENIC instead of checking for individual
Ingenic SoCs.
Additionally, I added a #define for the UART0 address in-code and
dropped the <asm/mach-jz4740/base.h> include, for the reason that this
include file is slowly being phased out as the whole platform is being
moved to devicetree.
Fixes: 9be5f3e92ed5 ("MIPS: ingenic: Initial JZ4770 support")
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # 4.16
Patchwork: https://patchwork.linux-mips.org/patch/18957/
Signed-off-by: James Hogan <jhogan@kernel.org>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/boot/compressed/uart-16550.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/mips/boot/compressed/uart-16550.c b/arch/mips/boot/compressed/uart-16550.c index b3043c08f769..aee8d7b8f091 100644 --- a/arch/mips/boot/compressed/uart-16550.c +++ b/arch/mips/boot/compressed/uart-16550.c @@ -18,9 +18,9 @@ #define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset)) #endif -#if defined(CONFIG_MACH_JZ4740) || defined(CONFIG_MACH_JZ4780) -#include <asm/mach-jz4740/base.h> -#define PORT(offset) (CKSEG1ADDR(JZ4740_UART0_BASE_ADDR) + (4 * offset)) +#ifdef CONFIG_MACH_INGENIC +#define INGENIC_UART0_BASE_ADDR 0x10030000 +#define PORT(offset) (CKSEG1ADDR(INGENIC_UART0_BASE_ADDR) + (4 * offset)) #endif #ifdef CONFIG_CPU_XLR |