diff options
| author |   Florian Fainelli <florian@openwrt.org> | 2011-11-16 19:11:12 +0100 |
|---|---|---|
| committer |   Ralf Baechle <ralf@linux-mips.org> | 2011-12-07 22:03:04 +0000 |
| commit | e1c96c8620539f056291fe42f742f331f5d291b1 (patch) | |
| tree | bcb161d447e8029bf8be300254afbbc9e63af7c6 /arch/mips | |
| parent | MIPS: BCM63xx: Fix SDRAM size computation for BCM6345 (diff) | |
| download | linux-dev-e1c96c8620539f056291fe42f742f331f5d291b1.tar.xz linux-dev-e1c96c8620539f056291fe42f742f331f5d291b1.zip | |
MIPS: BCM63xx: Remove BCM6345 hacks to read base boot address
Though BCM6345 does not technically have the same MPI register layout
than the other SoCs, reading the chip-select registers is done the same
way, and particularly for chip-select 0, which is the boot flash.
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3009/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/bcm63xx/boards/board_bcm963xx.c | 21 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 2 |
2 files changed, 7 insertions, 16 deletions
diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c index 40b223b603be..ac948c25c9f0 100644 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -709,15 +709,9 @@ void __init board_prom_init(void) char cfe_version[32]; u32 val; - /* read base address of boot chip select (0) - * 6345 does not have MPI but boots from standard - * MIPS Flash address */ - if (BCMCPU_IS_6345()) - val = 0x1fc00000; - else { - val = bcm_mpi_readl(MPI_CSBASE_REG(0)); - val &= MPI_CSBASE_BASE_MASK; - } + /* read base address of boot chip select (0) */ + val = bcm_mpi_readl(MPI_CSBASE_REG(0)); + val &= MPI_CSBASE_BASE_MASK; boot_addr = (u8 *)KSEG1ADDR(val); /* dump cfe version */ @@ -893,12 +887,9 @@ int __init board_register_devices(void) bcm63xx_dsp_register(&board.dsp); /* read base address of boot chip select (0) */ - if (BCMCPU_IS_6345()) - val = 0x1fc00000; - else { - val = bcm_mpi_readl(MPI_CSBASE_REG(0)); - val &= MPI_CSBASE_BASE_MASK; - } + val = bcm_mpi_readl(MPI_CSBASE_REG(0)); + val &= MPI_CSBASE_BASE_MASK; + mtd_resources[0].start = val; mtd_resources[0].end = 0x1FFFFFFF; diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h index 23403a32c158..5b8d15bb5fe8 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h @@ -215,7 +215,7 @@ enum bcm63xx_regs_set { #define BCM_6345_ENETDMAS_BASE (0xfffe2a00) #define BCM_6345_ENETSW_BASE (0xdeadbeef) #define BCM_6345_PCMCIA_BASE (0xfffe2028) -#define BCM_6345_MPI_BASE (0xdeadbeef) +#define BCM_6345_MPI_BASE (0xfffe2000) #define BCM_6345_OHCI0_BASE (0xfffe2100) #define BCM_6345_OHCI_PRIV_BASE (0xfffe2200) #define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) |