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| author |   David Howells <dhowells@redhat.com> | 2018-03-08 09:48:46 +0000 |
|---|---|---|
| committer |   Arnd Bergmann <arnd@arndb.de> | 2018-03-09 23:19:56 +0100 |
| commit | 739d875dd6982618020d30f58f8acf10f6076e6d (patch) | |
| tree | 13deb11d5b2078e49d4e5b6175e5846a22a04b95 /arch/mn10300/include/asm/cache.h | |
| parent | Merge tag 'metag_remove_2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/jhogan/metag into asm-generic (diff) | |
| download | linux-dev-739d875dd6982618020d30f58f8acf10f6076e6d.tar.xz linux-dev-739d875dd6982618020d30f58f8acf10f6076e6d.zip | |
mn10300: Remove the architecture
Remove the MN10300 arch as the hardware is defunct.
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: David Howells <dhowells@redhat.com>
cc: Masahiro Yamada <yamada.masahiro@socionext.com>
cc: linux-am33-list@redhat.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/mn10300/include/asm/cache.h')
| -rw-r--r-- | arch/mn10300/include/asm/cache.h | 60 |
1 files changed, 0 insertions, 60 deletions
diff --git a/arch/mn10300/include/asm/cache.h b/arch/mn10300/include/asm/cache.h deleted file mode 100644 index f29cde2cfc91..000000000000 --- a/arch/mn10300/include/asm/cache.h +++ /dev/null @@ -1,60 +0,0 @@ -/* MN10300 cache management registers - * - * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ - -#ifndef _ASM_CACHE_H -#define _ASM_CACHE_H - -#include <asm/cpu-regs.h> -#include <proc/cache.h> - -#ifndef __ASSEMBLY__ -#define L1_CACHE_DISPARITY (L1_CACHE_NENTRIES * L1_CACHE_BYTES) -#else -#define L1_CACHE_DISPARITY L1_CACHE_NENTRIES * L1_CACHE_BYTES -#endif - -#define ARCH_DMA_MINALIGN L1_CACHE_BYTES - -/* data cache purge registers - * - read from the register to unconditionally purge that cache line - * - write address & 0xffffff00 to conditionally purge that cache line - * - clear LSB to request invalidation as well - */ -#define DCACHE_PURGE(WAY, ENTRY) \ - __SYSREG(0xc8400000 + (WAY) * L1_CACHE_WAYDISP + \ - (ENTRY) * L1_CACHE_BYTES, u32) - -#define DCACHE_PURGE_WAY0(ENTRY) \ - __SYSREG(0xc8400000 + 0 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32) -#define DCACHE_PURGE_WAY1(ENTRY) \ - __SYSREG(0xc8400000 + 1 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32) -#define DCACHE_PURGE_WAY2(ENTRY) \ - __SYSREG(0xc8400000 + 2 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32) -#define DCACHE_PURGE_WAY3(ENTRY) \ - __SYSREG(0xc8400000 + 3 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32) - -/* instruction cache access registers */ -#define ICACHE_DATA(WAY, ENTRY, OFF) \ - __SYSREG(0xc8000000 + (WAY) * L1_CACHE_WAYDISP + \ - (ENTRY) * L1_CACHE_BYTES + (OFF) * 4, u32) -#define ICACHE_TAG(WAY, ENTRY) \ - __SYSREG(0xc8100000 + (WAY) * L1_CACHE_WAYDISP + \ - (ENTRY) * L1_CACHE_BYTES, u32) - -/* data cache access registers */ -#define DCACHE_DATA(WAY, ENTRY, OFF) \ - __SYSREG(0xc8200000 + (WAY) * L1_CACHE_WAYDISP + \ - (ENTRY) * L1_CACHE_BYTES + (OFF) * 4, u32) -#define DCACHE_TAG(WAY, ENTRY) \ - __SYSREG(0xc8300000 + (WAY) * L1_CACHE_WAYDISP + \ - (ENTRY) * L1_CACHE_BYTES, u32) - -#endif /* _ASM_CACHE_H */ |