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| author |   John David Anglin <dave.anglin@bell.net> | 2019-04-14 19:20:40 -0400 |
|---|---|---|
| committer |   Helge Deller <deller@gmx.de> | 2019-05-03 23:47:40 +0200 |
| commit | 9e5c602186a692a7e848c0da17aed40f49d30519 (patch) | |
| tree | 845499e6cc5d1ee17c786233d9a427ab44c2bb6b /arch/parisc/include/asm/spinlock.h | |
| parent | parisc: Remove lock code to serialize TLB operations in pacache.S (diff) | |
| download | linux-dev-9e5c602186a692a7e848c0da17aed40f49d30519.tar.xz linux-dev-9e5c602186a692a7e848c0da17aed40f49d30519.zip | |
parisc: Use ldcw instruction for SMP spinlock release barrier
There are only a couple of instructions that can function as a memory
barrier on parisc. Currently, we use the sync instruction as a memory
barrier when releasing a spinlock. However, the ldcw instruction is a
better barrier when we have a handy memory location since it operates in
the cache on coherent machines.
This patch updates the spinlock release code to use ldcw. I also
changed the "stw,ma" instructions to "stw" instructions as it is not an
adequate barrier.
Signed-off-by: John David Anglin <dave.anglin@bell.net>
Signed-off-by: Helge Deller <deller@gmx.de>
Diffstat (limited to 'arch/parisc/include/asm/spinlock.h')
| -rw-r--r-- | arch/parisc/include/asm/spinlock.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/parisc/include/asm/spinlock.h b/arch/parisc/include/asm/spinlock.h index 8a63515f03bf..197d2247e4db 100644 --- a/arch/parisc/include/asm/spinlock.h +++ b/arch/parisc/include/asm/spinlock.h @@ -37,7 +37,11 @@ static inline void arch_spin_unlock(arch_spinlock_t *x) volatile unsigned int *a; a = __ldcw_align(x); +#ifdef CONFIG_SMP + (void) __ldcw(a); +#else mb(); +#endif *a = 1; } |