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| author |   Helge Deller <deller@gmx.de> | 2015-12-21 10:00:49 +0100 |
|---|---|---|
| committer | Helge Deller <deller@gmx.de> | 2016-01-12 22:03:21 +0100 |
| commit | 602c9c9a01a4f0ef091295ac75c74c7fe94d69a4 (patch) | |
| tree | 71e93e3b04ebda62349811202f0dff522a89bc71 /arch/parisc | |
| parent | Linux 4.4 (diff) | |
| download | linux-dev-602c9c9a01a4f0ef091295ac75c74c7fe94d69a4.tar.xz linux-dev-602c9c9a01a4f0ef091295ac75c74c7fe94d69a4.zip | |
parisc: Initialize PCI bridge cache line and default latency
PCI controllers and pci-pci bridges may have not been fully initialized
regarding cache line and defaul latency.
This partly reverts
commit 5f0e9b4 ("parisc: Remove unused pcibios_init_bus()")
Signed-off-by: Helge Deller <deller@gmx.de>
Diffstat (limited to 'arch/parisc')
| -rw-r--r-- | arch/parisc/include/asm/pci.h | 1 | ||||
| -rw-r--r-- | arch/parisc/kernel/pci.c | 26 |
2 files changed, 27 insertions, 0 deletions
diff --git a/arch/parisc/include/asm/pci.h b/arch/parisc/include/asm/pci.h index 71889ea72740..89c53bfff055 100644 --- a/arch/parisc/include/asm/pci.h +++ b/arch/parisc/include/asm/pci.h @@ -167,6 +167,7 @@ static inline void pcibios_register_hba(struct pci_hba_data *x) { } #endif +extern void pcibios_init_bridge(struct pci_dev *); /* * pcibios_assign_all_busses() is used in drivers/pci/pci.c:pci_do_scan_bus() diff --git a/arch/parisc/kernel/pci.c b/arch/parisc/kernel/pci.c index c99f3dde455c..0903c6abd7a4 100644 --- a/arch/parisc/kernel/pci.c +++ b/arch/parisc/kernel/pci.c @@ -170,6 +170,32 @@ void pcibios_set_master(struct pci_dev *dev) (0x80 << 8) | pci_cache_line_size); } +/* + * pcibios_init_bridge() initializes cache line and default latency + * for pci controllers and pci-pci bridges + */ +void __init pcibios_init_bridge(struct pci_dev *dev) +{ + unsigned short bridge_ctl, bridge_ctl_new; + + /* We deal only with pci controllers and pci-pci bridges. */ + if (!dev || (dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) + return; + + /* PCI-PCI bridge - set the cache line and default latency + * (32) for primary and secondary buses. + */ + pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 32); + + pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bridge_ctl); + + bridge_ctl_new = bridge_ctl | PCI_BRIDGE_CTL_PARITY | + PCI_BRIDGE_CTL_SERR | PCI_BRIDGE_CTL_MASTER_ABORT; + dev_info(&dev->dev, "Changing bridge control from 0x%08x to 0x%08x\n", + bridge_ctl, bridge_ctl_new); + + pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bridge_ctl_new); +} /* * pcibios align resources() is called every time generic PCI code |