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| author |   Arnd Bergmann <arnd@arndb.de> | 2014-12-30 11:17:07 +0100 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2014-12-30 15:27:20 +0100 |
| commit | 7ebdfaa52d15b947503f76474477f92854796d96 (patch) | |
| tree | 27cd7acfcd264e8d643db86185f9e3a33a5cf367 /arch/powerpc/boot/dts/fsl/t2081si-post.dtsi | |
| parent | clocksource: arch_timer: Only use the virtual counter (CNTVCT) on arm64 (diff) | |
| parent | ARM: mvebu: Fix pinctrl configuration for Armada 370 DB (diff) | |
| download | linux-dev-7ebdfaa52d15b947503f76474477f92854796d96.tar.xz linux-dev-7ebdfaa52d15b947503f76474477f92854796d96.zip | |
Merge tag 'mvebu-fixes-3.19' of git://git.infradead.org/linux-mvebu into fixes
Pull "Fixes for 3.19" from Andrew Lunn:
Jason is taking a back seat this cycle and i'm doing all the patch
wrangling for mvebu.
* tag 'mvebu-fixes-3.19' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: Fix pinctrl configuration for Armada 370 DB
Also update to Linux 3.19-rc1, which this was based on.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/powerpc/boot/dts/fsl/t2081si-post.dtsi')
| -rw-r--r-- | arch/powerpc/boot/dts/fsl/t2081si-post.dtsi | 29 |
1 files changed, 2 insertions, 27 deletions
diff --git a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi index aecee9690a88..1ce91e3485a9 100644 --- a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi @@ -305,34 +305,9 @@ fsl,liodn-bits = <12>; }; - clockgen: global-utilities@e1000 { +/include/ "qoriq-clockgen2.dtsi" + global-utilities@e1000 { compatible = "fsl,t2080-clockgen", "fsl,qoriq-clockgen-2.0"; - ranges = <0x0 0xe1000 0x1000>; - reg = <0xe1000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - sysclk: sysclk { - #clock-cells = <0>; - compatible = "fsl,qoriq-sysclk-2.0"; - clock-output-names = "sysclk", "fixed-clock"; - }; - - pll0: pll0@800 { - #clock-cells = <1>; - reg = <0x800 4>; - compatible = "fsl,qoriq-core-pll-2.0"; - clocks = <&sysclk>; - clock-output-names = "pll0", "pll0-div2", "pll0-div4"; - }; - - pll1: pll1@820 { - #clock-cells = <1>; - reg = <0x820 4>; - compatible = "fsl,qoriq-core-pll-2.0"; - clocks = <&sysclk>; - clock-output-names = "pll1", "pll1-div2", "pll1-div4"; - }; mux0: mux0@0 { #clock-cells = <0>; |