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| author |   Minghuan Lian <Minghuan.Lian@freescale.com> | 2013-07-31 10:59:07 +0800 |
|---|---|---|
| committer |   Scott Wood <scottwood@freescale.com> | 2013-10-28 21:11:14 -0500 |
| commit | 0e3d4373b8a7757a8f5187f5cabafb6aceff469b (patch) | |
| tree | 74108e69667ae0866e066fc63f86f9d10b039793 /arch/powerpc/boot/dts/fsl | |
| parent | powerpc/booke: clear DBCR0_BT in user_disable_single_step() (diff) | |
| download | linux-dev-0e3d4373b8a7757a8f5187f5cabafb6aceff469b.tar.xz linux-dev-0e3d4373b8a7757a8f5187f5cabafb6aceff469b.zip | |
powerpc/dts: fix sRIO error interrupt for b4860
For B4 platform, MPIC EISR register is in reversed bitmap order,
instead of "Error interrupt source 0-31. Bit 0 represents SRC0."
the correct ordering is "Error interrupt source 0-31. Bit 0
represents SRC31." This patch is to fix sRIO EISR bit value
of error interrupt in dts node.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'arch/powerpc/boot/dts/fsl')
| -rw-r--r-- | arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi index e5cf6c81dd66..981397518fc6 100644 --- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi @@ -41,7 +41,7 @@ &rio { compatible = "fsl,srio"; - interrupts = <16 2 1 11>; + interrupts = <16 2 1 20>; #address-cells = <2>; #size-cells = <2>; fsl,iommu-parent = <&pamu0>; |