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| author |   Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> | 2018-03-26 15:34:49 +0530 |
|---|---|---|
| committer |   Michael Ellerman <mpe@ellerman.id.au> | 2018-03-31 00:10:38 +1100 |
| commit | c2b4d8b7417a59b7f9a52d0d8402f5257cbbd398 (patch) | |
| tree | 1494c8180465b2cfe2df7e97e7ee668f5974a4a6 /arch/powerpc/include/asm/book3s/64/hash-64k.h | |
| parent | powerpc/mm: Add support for handling > 512TB address in SLB miss (diff) | |
| download | linux-dev-c2b4d8b7417a59b7f9a52d0d8402f5257cbbd398.tar.xz linux-dev-c2b4d8b7417a59b7f9a52d0d8402f5257cbbd398.zip | |
powerpc/mm/hash64: Increase the VA range
This patch increases the max virtual (effective) address value to 4PB.
With 4K page size config we continue to limit ourself to 64TB.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
[mpe: Keep the H_PGTABLE_RANGE test, update it to work]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/include/asm/book3s/64/hash-64k.h')
| -rw-r--r-- | arch/powerpc/include/asm/book3s/64/hash-64k.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc/include/asm/book3s/64/hash-64k.h index f7a4f5cbf63e..eb393135d054 100644 --- a/arch/powerpc/include/asm/book3s/64/hash-64k.h +++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h @@ -4,7 +4,7 @@ #define H_PTE_INDEX_SIZE 8 #define H_PMD_INDEX_SIZE 10 -#define H_PUD_INDEX_SIZE 7 +#define H_PUD_INDEX_SIZE 10 #define H_PGD_INDEX_SIZE 8 /* |