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| author |   Anju T Sudhakar <anju@linux.vnet.ibm.com> | 2020-07-13 20:16:23 +0530 |
|---|---|---|
| committer |   Michael Ellerman <mpe@ellerman.id.au> | 2020-07-16 13:12:46 +1000 |
| commit | 77ca3951cc37727ae8361d583a30da7a1b84e427 (patch) | |
| tree | c4bac83d1ef6b6d7b20d2b2aebd0f2192a72ff7f /arch/powerpc/include/asm/imc-pmu.h | |
| parent | powerpc/Kconfig: Replace HTTP links with HTTPS ones (diff) | |
| download | linux-dev-77ca3951cc37727ae8361d583a30da7a1b84e427.tar.xz linux-dev-77ca3951cc37727ae8361d583a30da7a1b84e427.zip | |
powerpc/perf: Add kernel support for new MSR[HV PR] bits in trace-imc
IMC trace-mode record has MSR[HV PR] bits added in the third DW.
These bits can be used to set the cpumode for the instruction pointer
captured in each sample.
Add support in kernel to use these bits to set the cpumode for
each sample.
Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com>
Signed-off-by: Madhavan Srinivasan <maddy@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200713144623.508695-1-maddy@linux.ibm.com
Diffstat (limited to 'arch/powerpc/include/asm/imc-pmu.h')
| -rw-r--r-- | arch/powerpc/include/asm/imc-pmu.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/imc-pmu.h b/arch/powerpc/include/asm/imc-pmu.h index 4da4fcba0684..4f897993b710 100644 --- a/arch/powerpc/include/asm/imc-pmu.h +++ b/arch/powerpc/include/asm/imc-pmu.h @@ -99,6 +99,11 @@ struct trace_imc_data { */ #define IMC_TRACE_RECORD_TB1_MASK 0x3ffffffffffULL +/* + * Bit 0:1 in third DW of IMC trace record + * specifies the MSR[HV PR] values. + */ +#define IMC_TRACE_RECORD_VAL_HVPR(x) ((x) >> 62) /* * Device tree parser code detects IMC pmu support and |