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| author |   Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> | 2018-05-29 19:58:41 +0530 |
|---|---|---|
| committer |   Michael Ellerman <mpe@ellerman.id.au> | 2018-06-03 20:40:34 +1000 |
| commit | bd5050e38aec3055ff4257ade987d808ac93b582 (patch) | |
| tree | be6977a946ecb940ccd15a099689e86169be1bc0 /arch/powerpc/include/asm/nohash/64/pgtable.h | |
| parent | powerpc/mm: Change function prototype (diff) | |
| download | linux-dev-bd5050e38aec3055ff4257ade987d808ac93b582.tar.xz linux-dev-bd5050e38aec3055ff4257ade987d808ac93b582.zip | |
powerpc/mm/radix: Change pte relax sequence to handle nest MMU hang
When relaxing access (read -> read_write update), pte needs to be marked invalid
to handle a nest MMU bug. We also need to do a tlb flush after the pte is
marked invalid before updating the pte with new access bits.
We also move tlb flush to platform specific __ptep_set_access_flags. This will
help us to gerid of unnecessary tlb flush on BOOK3S 64 later. We don't do that
in this patch. This also helps in avoiding multiple tlbies with coprocessor
attached.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/include/asm/nohash/64/pgtable.h')
| -rw-r--r-- | arch/powerpc/include/asm/nohash/64/pgtable.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/nohash/64/pgtable.h b/arch/powerpc/include/asm/nohash/64/pgtable.h index 180161d714fb..dd0c7236208f 100644 --- a/arch/powerpc/include/asm/nohash/64/pgtable.h +++ b/arch/powerpc/include/asm/nohash/64/pgtable.h @@ -304,6 +304,8 @@ static inline void __ptep_set_access_flags(struct vm_area_struct *vma, unsigned long old = pte_val(*ptep); *ptep = __pte(old | bits); #endif + + flush_tlb_page(vma, address); } #define __HAVE_ARCH_PTE_SAME |