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| author |   Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2017-07-24 14:28:00 +1000 |
|---|---|---|
| committer |   Michael Ellerman <mpe@ellerman.id.au> | 2017-08-18 13:07:16 +1000 |
| commit | 1a92a80ad386a1a6e3b36d576d52a1a456394b70 (patch) | |
| tree | 7c23e2a850b9353cf6debd63dcde4c073b370f56 /arch/powerpc/include/asm/pgtable-types.h | |
| parent | powerpc: Fix VSX enabling/flushing to also test MSR_FP and MSR_VEC (diff) | |
| download | linux-dev-1a92a80ad386a1a6e3b36d576d52a1a456394b70.tar.xz linux-dev-1a92a80ad386a1a6e3b36d576d52a1a456394b70.zip | |
powerpc/mm: Ensure cpumask update is ordered
There is no guarantee that the various isync's involved with
the context switch will order the update of the CPU mask with
the first TLB entry for the new context being loaded by the HW.
Be safe here and add a memory barrier to order any subsequent
load/store which may bring entries into the TLB.
The corresponding barrier on the other side already exists as
pte updates use pte_xchg() which uses __cmpxchg_u64 which has
a sync after the atomic operation.
Cc: stable@vger.kernel.org
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
[mpe: Add comments in the code]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/include/asm/pgtable-types.h')
| -rw-r--r-- | arch/powerpc/include/asm/pgtable-types.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/pgtable-types.h b/arch/powerpc/include/asm/pgtable-types.h index 8bd3b13fe2fb..369a164b545c 100644 --- a/arch/powerpc/include/asm/pgtable-types.h +++ b/arch/powerpc/include/asm/pgtable-types.h @@ -62,6 +62,7 @@ static inline bool pte_xchg(pte_t *ptep, pte_t old, pte_t new) { unsigned long *p = (unsigned long *)ptep; + /* See comment in switch_mm_irqs_off() */ return pte_val(old) == __cmpxchg_u64(p, pte_val(old), pte_val(new)); } #endif |