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| author |   Kokoris, Ioannis <ioannis.kokoris@siemens-enterprise.com> | 2011-11-11 17:05:11 +0100 |
|---|---|---|
| committer |   Kumar Gala <galak@kernel.crashing.org> | 2012-07-10 07:08:58 -0500 |
| commit | e65650e6c3eb67226eda80a21f62b7aa145878f4 (patch) | |
| tree | 9fe3c6ecf29385a4890c83724ef5be42b1e0328d /arch/powerpc/include/asm/qe.h | |
| parent | powerpc/85xx: MPC8572DS - Update the MSI interrupts into 4-cell format (diff) | |
| download | linux-dev-e65650e6c3eb67226eda80a21f62b7aa145878f4.tar.xz linux-dev-e65650e6c3eb67226eda80a21f62b7aa145878f4.zip | |
powerpc/qe: set IReady in QE Microcode Upload
QE Microcode Initialization using qe_upload_microcode() does not work on
P1021 if the IRAM-Ready register is not set after the microcode upload. Add
a definition for the "I-RAM Ready" register and sets it upon microcode
upload completion.
Signed-off-by: Ioannis Kokkoris <ioannis.kokoris@siemens-enterprise.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include/asm/qe.h')
| -rw-r--r-- | arch/powerpc/include/asm/qe.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/qe.h b/arch/powerpc/include/asm/qe.h index 5e0b6d511e14..229571a49391 100644 --- a/arch/powerpc/include/asm/qe.h +++ b/arch/powerpc/include/asm/qe.h @@ -499,6 +499,7 @@ enum comm_dir { /* I-RAM */ #define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */ #define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */ +#define QE_IRAM_READY 0x80000000 /* Ready */ /* UPC */ #define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */ |