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authorYork Sun <yorksun@freescale.com>2012-09-29 16:44:35 -0700
committerKumar Gala <galak@kernel.crashing.org>2012-11-25 07:00:31 -0600
commitbc15236fbed1e017b465e38a9d2092393778a2f7 (patch)
treea367f8260c54d925f01c78d2f7f9d83292d4f84a /arch/powerpc/include
parentpowerpc/fsl-pci: Add PCI controller ATMU PM support (diff)
downloadlinux-dev-bc15236fbed1e017b465e38a9d2092393778a2f7.tar.xz
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powerpc/mpc85xx: Change spin table to cached memory
ePAPR v1.1 requires the spin table to be in cached memory. So we need to change the call argument of ioremap to enable cache and coherence. We also flush the cache after writing to spin table to keep it compatible with previous cache-inhibit spin table. Flushing before and after accessing spin table is recommended by ePAPR. Signed-off-by: York Sun <yorksun@freescale.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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