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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2008-12-18 19:13:38 +0000
committerPaul Mackerras <paulus@samba.org>2008-12-21 14:21:16 +1100
commitf048aace29e007f2b642097e2da8231e0e9cce2d (patch)
tree5e99b1d1d37817703132e97388994386a7bee8da /arch/powerpc/kernel/ppc_ksyms.c
parentpowerpc/mm: Introduce MMU features (diff)
downloadlinux-dev-f048aace29e007f2b642097e2da8231e0e9cce2d.tar.xz
linux-dev-f048aace29e007f2b642097e2da8231e0e9cce2d.zip
powerpc/mm: Add SMP support to no-hash TLB handling
This commit moves the whole no-hash TLB handling out of line into a new tlb_nohash.c file, and implements some basic SMP support using IPIs and/or broadcast tlbivax instructions. Note that I'm using local invalidations for D->I cache coherency. At worst, if another processor is trying to execute the same and has the old entry in its TLB, it will just take a fault and re-do the TLB flush locally (it won't re-do the cache flush in any case). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/kernel/ppc_ksyms.c')
-rw-r--r--arch/powerpc/kernel/ppc_ksyms.c6
1 files changed, 0 insertions, 6 deletions
diff --git a/arch/powerpc/kernel/ppc_ksyms.c b/arch/powerpc/kernel/ppc_ksyms.c
index 341b3d3048e0..dcec1325d340 100644
--- a/arch/powerpc/kernel/ppc_ksyms.c
+++ b/arch/powerpc/kernel/ppc_ksyms.c
@@ -116,12 +116,6 @@ EXPORT_SYMBOL(giveup_spe);
#ifndef CONFIG_PPC64
EXPORT_SYMBOL(flush_instruction_cache);
-EXPORT_SYMBOL(flush_tlb_kernel_range);
-EXPORT_SYMBOL(flush_tlb_page);
-EXPORT_SYMBOL(_tlbie);
-#if defined(CONFIG_4xx) || defined(CONFIG_8xx) || defined(CONFIG_FSL_BOOKE)
-EXPORT_SYMBOL(_tlbil_va);
-#endif
#endif
EXPORT_SYMBOL(__flush_icache_range);
EXPORT_SYMBOL(flush_dcache_range);