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| author |   Christophe Leroy <christophe.leroy@c-s.fr> | 2019-01-25 12:34:20 +0000 |
|---|---|---|
| committer |   Michael Ellerman <mpe@ellerman.id.au> | 2019-02-22 00:10:16 +1100 |
| commit | 78ca1108b10927b3d068c8da91352b0f4cd01fc5 (patch) | |
| tree | 06e9414cb146b251eead7a86677eb2f251651ade /arch/powerpc/kernel | |
| parent | powerpc/603: don't handle PAGE_ACCESSED in TLB miss handlers. (diff) | |
| download | linux-dev-78ca1108b10927b3d068c8da91352b0f4cd01fc5.tar.xz linux-dev-78ca1108b10927b3d068c8da91352b0f4cd01fc5.zip | |
powerpc/book3s32: Reorder _PAGE_XXX flags to simplify TLB handling
For pages without _PAGE_USER, PP field is 00
For pages with _PAGE_USER, PP field is 10 for RW and 11 for RO.
This patch sets _PAGE_USER to 0x002 and _PAGE_RW to 0x001
is order to simplify TLB handling by reducing amount of shifts.
The location of _PAGE_PRESENT and _PAGE_HASHPTE doesn't matter
as they are only SW related flags.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/kernel')
| -rw-r--r-- | arch/powerpc/kernel/head_32.S | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S index fdb587c96a80..e7a5b312a7db 100644 --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S @@ -522,7 +522,6 @@ InstructionTLBMiss: andc. r1,r1,r0 /* check access & ~permission */ bne- InstructionAddressInvalid /* return if access not permitted */ /* Convert linux-style PTE to low word of PPC-style PTE */ - rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */ ori r1, r1, 0xe05 /* clear out reserved bits */ andc r1, r0, r1 /* PP = user? 2 : 0 */ BEGIN_FTR_SECTION @@ -590,8 +589,7 @@ DataLoadTLBMiss: * we would need to update the pte atomically with lwarx/stwcx. */ /* Convert linux-style PTE to low word of PPC-style PTE */ - rlwinm r1,r0,32-10,31,31 /* _PAGE_RW -> PP lsb */ - rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */ + rlwinm r1, r0, 0, 31, 31 /* _PAGE_RW -> PP lsb */ rlwimi r0,r0,32-1,31,31 /* _PAGE_USER -> PP lsb */ ori r1,r1,0xe04 /* clear out reserved bits */ andc r1,r0,r1 /* PP = user? rw? 2: 3: 0 */ @@ -670,7 +668,6 @@ DataStoreTLBMiss: * we would need to update the pte atomically with lwarx/stwcx. */ /* Convert linux-style PTE to low word of PPC-style PTE */ - rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */ li r1,0xe05 /* clear out reserved bits & PP lsb */ andc r1,r0,r1 /* PP = user? 2: 0 */ BEGIN_FTR_SECTION |