diff options
| author |   Paul Mackerras <paulus@samba.org> | 2011-06-29 00:18:26 +0000 |
|---|---|---|
| committer |   Avi Kivity <avi@redhat.com> | 2011-07-12 13:16:48 +0300 |
| commit | b01c8b54a1a271c0fc4243845927fe1d250767a3 (patch) | |
| tree | 4e818a41d602aa07cbdc06eca9372b9b95c533a4 /arch/powerpc/kvm/book3s_segment.S | |
| parent | KVM: PPC: Split out code from book3s.c into book3s_pr.c (diff) | |
| download | linux-dev-b01c8b54a1a271c0fc4243845927fe1d250767a3.tar.xz linux-dev-b01c8b54a1a271c0fc4243845927fe1d250767a3.zip | |
powerpc, KVM: Rework KVM checks in first-level interrupt handlers
Instead of branching out-of-line with the DO_KVM macro to check if we
are in a KVM guest at the time of an interrupt, this moves the KVM
check inline in the first-level interrupt handlers. This speeds up
the non-KVM case and makes sure that none of the interrupt handlers
are missing the check.
Because the first-level interrupt handlers are now larger, some things
had to be move out of line in exceptions-64s.S.
This all necessitated some minor changes to the interrupt entry code
in KVM. This also streamlines the book3s_32 KVM test.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'arch/powerpc/kvm/book3s_segment.S')
| -rw-r--r-- | arch/powerpc/kvm/book3s_segment.S | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/powerpc/kvm/book3s_segment.S b/arch/powerpc/kvm/book3s_segment.S index 451264274b8c..4a623eb28a53 100644 --- a/arch/powerpc/kvm/book3s_segment.S +++ b/arch/powerpc/kvm/book3s_segment.S @@ -125,6 +125,9 @@ kvmppc_handler_trampoline_enter_end: .global kvmppc_handler_trampoline_exit kvmppc_handler_trampoline_exit: +.global kvmppc_interrupt +kvmppc_interrupt: + /* Register usage at this point: * * SPRG_SCRATCH0 = guest R13 @@ -155,12 +158,16 @@ kvmppc_handler_trampoline_exit: PPC_LL r2, (SHADOW_VCPU_OFF + SVCPU_HOST_R2)(r13) /* Save guest PC and MSR */ +#ifdef CONFIG_PPC64 +BEGIN_FTR_SECTION andi. r0,r12,0x2 beq 1f mfspr r3,SPRN_HSRR0 mfspr r4,SPRN_HSRR1 andi. r12,r12,0x3ffd b 2f +END_FTR_SECTION_IFSET(CPU_FTR_HVMODE_206) +#endif 1: mfsrr0 r3 mfsrr1 r4 2: |