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| author |   Valentine Barshak <vbarshak@ru.mvista.com> | 2007-10-26 04:16:40 +1000 |
|---|---|---|
| committer |   Josh Boyer <jwboyer@linux.vnet.ibm.com> | 2007-11-01 07:13:43 -0500 |
| commit | d1dfc35d3a62122b85ca975b80dcbf4a0da0bebc (patch) | |
| tree | 61a5b0969dc452f77d3ad87ca851f1f4237a2219 /arch/powerpc/mm/40x_mmu.c | |
| parent | [POWERPC] Uartlite: speed up console output (diff) | |
| download | linux-dev-d1dfc35d3a62122b85ca975b80dcbf4a0da0bebc.tar.xz linux-dev-d1dfc35d3a62122b85ca975b80dcbf4a0da0bebc.zip | |
[POWERPC] 4xx: Workaround for the 440EP(x)/GR(x) processors identical PVR issue.
PowerPC 440EP(x) 440GR(x) processors have the same PVR values, since
they have identical cores. However, FPU is not supported on GR(x) and
enabling APU instruction broadcast in the CCR0 register (to enable FPU)
may cause unpredictable results. There's no safe way to detect FPU
support at runtime. This patch provides a workarund for the issue.
We use a POWER6 "logical PVR approach". First, we identify all EP(x)
and GR(x) processors as GR(x) ones (which is safe). Then we check
the device tree cpu path. If we have a EP(x) processor entry,
we call identify_cpu again with PVR | 0x8. This bit is always 0
in the real PVR. This way we enable FPU only for 440EP(x).
Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'arch/powerpc/mm/40x_mmu.c')
0 files changed, 0 insertions, 0 deletions