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| author |   Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> | 2016-11-28 11:47:02 +0530 |
|---|---|---|
| committer |   Michael Ellerman <mpe@ellerman.id.au> | 2016-11-28 22:44:33 +1100 |
| commit | b3603e174fc81598e8b060d5e9aafe19ee6e65cf (patch) | |
| tree | c88370d7804b2a874ccc1bae4dd95d58d07174da /arch/powerpc/mm/pgtable-book3s64.c | |
| parent | powerpc/mm: Add radix__tlb_flush_pte_p9_dd1() (diff) | |
| download | linux-dev-b3603e174fc81598e8b060d5e9aafe19ee6e65cf.tar.xz linux-dev-b3603e174fc81598e8b060d5e9aafe19ee6e65cf.zip | |
powerpc/mm: update radix__ptep_set_access_flag to not do full mm tlb flush
When we are updating a pte, we just need to flush the tlb mapping
that pte. Right now we do a full mm flush because we don't track the page
size. Now that we have page size details in pte use that to do the
optimized flush
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/mm/pgtable-book3s64.c')
| -rw-r--r-- | arch/powerpc/mm/pgtable-book3s64.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/powerpc/mm/pgtable-book3s64.c b/arch/powerpc/mm/pgtable-book3s64.c index f4f437cbabf1..ebf9782bacf9 100644 --- a/arch/powerpc/mm/pgtable-book3s64.c +++ b/arch/powerpc/mm/pgtable-book3s64.c @@ -35,7 +35,8 @@ int pmdp_set_access_flags(struct vm_area_struct *vma, unsigned long address, #endif changed = !pmd_same(*(pmdp), entry); if (changed) { - __ptep_set_access_flags(vma->vm_mm, pmdp_ptep(pmdp), pmd_pte(entry)); + __ptep_set_access_flags(vma->vm_mm, pmdp_ptep(pmdp), + pmd_pte(entry), address); flush_pmd_tlb_range(vma, address, address + HPAGE_PMD_SIZE); } return changed; |