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| author |   Hari Bathini <hbathini@linux.ibm.com> | 2022-06-10 21:25:50 +0530 |
|---|---|---|
| committer |   Michael Ellerman <mpe@ellerman.id.au> | 2022-06-29 19:37:08 +1000 |
| commit | 1e82dfaa7819f03f0b0022be7ca15bbc83090da1 (patch) | |
| tree | 37f5857b32825463b5deb8ca7875339d9dfe9412 /arch/powerpc/net/bpf_jit_comp64.c | |
| parent | powerpc/bpf/64: add support for atomic fetch operations (diff) | |
| download | linux-dev-1e82dfaa7819f03f0b0022be7ca15bbc83090da1.tar.xz linux-dev-1e82dfaa7819f03f0b0022be7ca15bbc83090da1.zip | |
powerpc/bpf/64: Add instructions for atomic_[cmp]xchg
This adds two atomic opcodes BPF_XCHG and BPF_CMPXCHG on ppc64, both
of which include the BPF_FETCH flag. The kernel's atomic_cmpxchg
operation fundamentally has 3 operands, but we only have two register
fields. Therefore the operand we compare against (the kernel's API
calls it 'old') is hard-coded to be BPF_REG_R0. Also, kernel's
atomic_cmpxchg returns the previous value at dst_reg + off. JIT the
same for BPF too with return value put in BPF_REG_0.
BPF_REG_R0 = atomic_cmpxchg(dst_reg + off, BPF_REG_R0, src_reg);
Signed-off-by: Hari Bathini <hbathini@linux.ibm.com>
Tested-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> (ppc64le)
Reviewed-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220610155552.25892-4-hbathini@linux.ibm.com
Diffstat (limited to 'arch/powerpc/net/bpf_jit_comp64.c')
| -rw-r--r-- | arch/powerpc/net/bpf_jit_comp64.c | 39 |
1 files changed, 34 insertions, 5 deletions
diff --git a/arch/powerpc/net/bpf_jit_comp64.c b/arch/powerpc/net/bpf_jit_comp64.c index c53236b3a8b1..29ee306d6302 100644 --- a/arch/powerpc/net/bpf_jit_comp64.c +++ b/arch/powerpc/net/bpf_jit_comp64.c @@ -360,6 +360,7 @@ int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context * u32 size = BPF_SIZE(code); u32 tmp1_reg = bpf_to_ppc(TMP_REG_1); u32 tmp2_reg = bpf_to_ppc(TMP_REG_2); + u32 save_reg, ret_reg; s16 off = insn[i].off; s32 imm = insn[i].imm; bool func_addr_fixed; @@ -778,6 +779,9 @@ emit_clear: */ case BPF_STX | BPF_ATOMIC | BPF_W: case BPF_STX | BPF_ATOMIC | BPF_DW: + save_reg = tmp2_reg; + ret_reg = src_reg; + /* Get offset into TMP_REG_1 */ EMIT(PPC_RAW_LI(tmp1_reg, off)); tmp_idx = ctx->idx * 4; @@ -808,6 +812,24 @@ emit_clear: case BPF_XOR | BPF_FETCH: EMIT(PPC_RAW_XOR(tmp2_reg, tmp2_reg, src_reg)); break; + case BPF_CMPXCHG: + /* + * Return old value in BPF_REG_0 for BPF_CMPXCHG & + * in src_reg for other cases. + */ + ret_reg = bpf_to_ppc(BPF_REG_0); + + /* Compare with old value in BPF_R0 */ + if (size == BPF_DW) + EMIT(PPC_RAW_CMPD(bpf_to_ppc(BPF_REG_0), tmp2_reg)); + else + EMIT(PPC_RAW_CMPW(bpf_to_ppc(BPF_REG_0), tmp2_reg)); + /* Don't set if different from old value */ + PPC_BCC_SHORT(COND_NE, (ctx->idx + 3) * 4); + fallthrough; + case BPF_XCHG: + save_reg = src_reg; + break; default: pr_err_ratelimited( "eBPF filter atomic op code %02x (@%d) unsupported\n", @@ -817,15 +839,22 @@ emit_clear: /* store new value */ if (size == BPF_DW) - EMIT(PPC_RAW_STDCX(tmp2_reg, tmp1_reg, dst_reg)); + EMIT(PPC_RAW_STDCX(save_reg, tmp1_reg, dst_reg)); else - EMIT(PPC_RAW_STWCX(tmp2_reg, tmp1_reg, dst_reg)); + EMIT(PPC_RAW_STWCX(save_reg, tmp1_reg, dst_reg)); /* we're done if this succeeded */ PPC_BCC_SHORT(COND_NE, tmp_idx); - /* For the BPF_FETCH variant, get old value into src_reg */ - if (imm & BPF_FETCH) - EMIT(PPC_RAW_MR(src_reg, _R0)); + if (imm & BPF_FETCH) { + EMIT(PPC_RAW_MR(ret_reg, _R0)); + /* + * Skip unnecessary zero-extension for 32-bit cmpxchg. + * For context, see commit 39491867ace5. + */ + if (size != BPF_DW && imm == BPF_CMPXCHG && + insn_is_zext(&insn[i + 1])) + addrs[++i] = ctx->idx * 4; + } break; /* |