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authorAthira Rajeev <atrajeev@linux.vnet.ibm.com>2020-07-17 10:38:15 -0400
committerMichael Ellerman <mpe@ellerman.id.au>2020-07-22 21:56:40 +1000
commit9d4fc86dcd510dab5521a6c891f9bf379b85a7e0 (patch)
tree7f885b485a5a633a65f94b79469afeb7619beec8 /arch/powerpc/perf/power8-pmu.c
parentKVM: PPC: Book3S HV: Cleanup updates for kvm vcpu MMCR (diff)
downloadlinux-dev-9d4fc86dcd510dab5521a6c891f9bf379b85a7e0.tar.xz
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powerpc/perf: Update Power PMU cache_events to u64 type
Events of type PERF_TYPE_HW_CACHE was described for Power PMU as: int (*cache_events)[type][op][result]; where type, op, result values unpacked from the event attribute config value is used to generate the raw event code at runtime. So far the event code values which used to create these cache-related events were within 32 bit and `int` type worked. In power10, some of the event codes are of 64-bit value and hence update the Power PMU cache_events to `u64` type in `power_pmu` struct. Also propagate this change to existing all PMU driver code paths which are using ppmu->cache_events. Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/1594996707-3727-4-git-send-email-atrajeev@linux.vnet.ibm.com
Diffstat (limited to 'arch/powerpc/perf/power8-pmu.c')
-rw-r--r--arch/powerpc/perf/power8-pmu.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c
index 3a5fcc20ff31..5282e8415ddf 100644
--- a/arch/powerpc/perf/power8-pmu.c
+++ b/arch/powerpc/perf/power8-pmu.c
@@ -253,7 +253,7 @@ static void power8_config_bhrb(u64 pmu_bhrb_filter)
* 0 means not supported, -1 means nonsensical, other values
* are event codes.
*/
-static int power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
+static u64 power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
[ C(L1D) ] = {
[ C(OP_READ) ] = {
[ C(RESULT_ACCESS) ] = PM_LD_REF_L1,