diff options
| author |   Liu Yu-B13201 <Yu.Liu@freescale.com> | 2010-01-13 22:13:17 +0000 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2010-01-21 01:17:54 -0800 |
| commit | c1fb8340d7a39346c08ec4b1db4fb432f02acd4c (patch) | |
| tree | f6e93360e9395ec758ab326af79fc27ee4fcda9f /arch/powerpc/platforms/85xx/mpc85xx_mds.c | |
| parent | dts/mpc8569mds: Cleanup tbi phy to support rtbi (diff) | |
| download | linux-dev-c1fb8340d7a39346c08ec4b1db4fb432f02acd4c.tar.xz linux-dev-c1fb8340d7a39346c08ec4b1db4fb432f02acd4c.zip | |
mpc8569mds: Add bscr setting for rtbi mode
Signed-off-by: Liu Yu <yu.liu@freescale.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/powerpc/platforms/85xx/mpc85xx_mds.c')
| -rw-r--r-- | arch/powerpc/platforms/85xx/mpc85xx_mds.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c index 21f61b8c445b..04ed2156db1c 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c @@ -237,6 +237,8 @@ static void __init mpc85xx_mds_setup_arch(void) } else if (machine_is(mpc8569_mds)) { #define BCSR7_UCC12_GETHnRST (0x1 << 2) #define BCSR8_UEM_MARVELL_RST (0x1 << 1) +#define BCSR_UCC_RGMII (0x1 << 6) +#define BCSR_UCC_RTBI (0x1 << 5) /* * U-Boot mangles interrupt polarity for Marvell PHYs, * so reset built-in and UEM Marvell PHYs, this puts @@ -247,6 +249,28 @@ static void __init mpc85xx_mds_setup_arch(void) setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST); clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST); + + for (np = NULL; (np = of_find_compatible_node(np, + "network", + "ucc_geth")) != NULL;) { + const unsigned int *prop; + int ucc_num; + + prop = of_get_property(np, "cell-index", NULL); + if (prop == NULL) + continue; + + ucc_num = *prop - 1; + + prop = of_get_property(np, "phy-connection-type", NULL); + if (prop == NULL) + continue; + + if (strcmp("rtbi", (const char *)prop) == 0) + clrsetbits_8(&bcsr_regs[7 + ucc_num], + BCSR_UCC_RGMII, BCSR_UCC_RTBI); + } + } iounmap(bcsr_regs); } |