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| author |   Cédric Le Goater <clg@kaod.org> | 2021-07-20 15:42:09 +0200 |
|---|---|---|
| committer |   Michael Ellerman <mpe@ellerman.id.au> | 2021-08-10 23:15:02 +1000 |
| commit | f5af0a978776b710f16dc99a85496b1e760bf9e0 (patch) | |
| tree | f11b8cfb23d59ceec4cc6718721f09d278481237 /arch/powerpc/sysdev/xive/native.c | |
| parent | KVM: PPC: Book3S HV: XIVE: Add a 'flags' field (diff) | |
| download | linux-dev-f5af0a978776b710f16dc99a85496b1e760bf9e0.tar.xz linux-dev-f5af0a978776b710f16dc99a85496b1e760bf9e0.zip | |
KVM: PPC: Book3S HV: XIVE: Add support for automatic save-restore
On P10, the feature doing an automatic "save & restore" of a VCPU
interrupt context is set by default in OPAL. When a VP context is
pulled out, the state of the interrupt registers are saved by the XIVE
interrupt controller under the internal NVP structure representing the
VP. This saves a costly store/load in guest entries and exits.
If OPAL advertises the "save & restore" feature in the device tree,
it should also have set the 'H' bit in the CAM line. Check that when
vCPUs are connected to their ICP in KVM before going any further.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210720134209.256133-3-clg@kaod.org
Diffstat (limited to 'arch/powerpc/sysdev/xive/native.c')
| -rw-r--r-- | arch/powerpc/sysdev/xive/native.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/powerpc/sysdev/xive/native.c b/arch/powerpc/sysdev/xive/native.c index 57e3f1540435..1aec282cd650 100644 --- a/arch/powerpc/sysdev/xive/native.c +++ b/arch/powerpc/sysdev/xive/native.c @@ -41,6 +41,7 @@ static u32 xive_queue_shift; static u32 xive_pool_vps = XIVE_INVALID_VP; static struct kmem_cache *xive_provision_cache; static bool xive_has_single_esc; +static bool xive_has_save_restore; int xive_native_populate_irq_data(u32 hw_irq, struct xive_irq_data *data) { @@ -588,6 +589,9 @@ bool __init xive_native_init(void) if (of_get_property(np, "single-escalation-support", NULL) != NULL) xive_has_single_esc = true; + if (of_get_property(np, "vp-save-restore", NULL)) + xive_has_save_restore = true; + /* Configure Thread Management areas for KVM */ for_each_possible_cpu(cpu) kvmppc_set_xive_tima(cpu, r.start, tima); @@ -752,6 +756,12 @@ bool xive_native_has_single_escalation(void) } EXPORT_SYMBOL_GPL(xive_native_has_single_escalation); +bool xive_native_has_save_restore(void) +{ + return xive_has_save_restore; +} +EXPORT_SYMBOL_GPL(xive_native_has_save_restore); + int xive_native_get_queue_info(u32 vp_id, u32 prio, u64 *out_qpage, u64 *out_qsize, |