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| author |   Kumar Gala <galak@freescale.com> | 2005-09-03 15:55:55 -0700 |
|---|---|---|
| committer |   Linus Torvalds <torvalds@evo.osdl.org> | 2005-09-05 00:06:00 -0700 |
| commit | bbde630b553d349307fe719486bc06f8cf9c1a2d (patch) | |
| tree | de7a71a39423c907301dd4eab6ccf31736227c24 /arch/ppc/kernel/cpu_setup_6xx.S | |
| parent | [PATCH] ppc32: export cacheable_memcpy() (diff) | |
| download | linux-dev-bbde630b553d349307fe719486bc06f8cf9c1a2d.tar.xz linux-dev-bbde630b553d349307fe719486bc06f8cf9c1a2d.zip | |
[PATCH] ppc32: Added cputable entry for 7448
Added cputable entry for 7448 as well adding it to checks for saving and
restoring of cpu state.
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/ppc/kernel/cpu_setup_6xx.S')
| -rw-r--r-- | arch/ppc/kernel/cpu_setup_6xx.S | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/ppc/kernel/cpu_setup_6xx.S b/arch/ppc/kernel/cpu_setup_6xx.S index 3fb1fb619d2c..bd037caa4055 100644 --- a/arch/ppc/kernel/cpu_setup_6xx.S +++ b/arch/ppc/kernel/cpu_setup_6xx.S @@ -327,6 +327,7 @@ _GLOBAL(__save_cpu_setup) cmplwi cr4,r3,0x8002 /* 7457 */ cmplwi cr5,r3,0x8003 /* 7447A */ cmplwi cr6,r3,0x7000 /* 750FX */ + cmplwi cr7,r3,0x8004 /* 7448 */ /* cr1 is 7400 || 7410 */ cror 4*cr1+eq,4*cr1+eq,4*cr2+eq /* cr0 is 74xx */ @@ -334,6 +335,7 @@ _GLOBAL(__save_cpu_setup) cror 4*cr0+eq,4*cr0+eq,4*cr4+eq cror 4*cr0+eq,4*cr0+eq,4*cr1+eq cror 4*cr0+eq,4*cr0+eq,4*cr5+eq + cror 4*cr0+eq,4*cr0+eq,4*cr7+eq bne 1f /* Backup 74xx specific regs */ mfspr r4,SPRN_MSSCR0 @@ -396,6 +398,7 @@ _GLOBAL(__restore_cpu_setup) cmplwi cr4,r3,0x8002 /* 7457 */ cmplwi cr5,r3,0x8003 /* 7447A */ cmplwi cr6,r3,0x7000 /* 750FX */ + cmplwi cr7,r3,0x8004 /* 7448 */ /* cr1 is 7400 || 7410 */ cror 4*cr1+eq,4*cr1+eq,4*cr2+eq /* cr0 is 74xx */ @@ -403,6 +406,7 @@ _GLOBAL(__restore_cpu_setup) cror 4*cr0+eq,4*cr0+eq,4*cr4+eq cror 4*cr0+eq,4*cr0+eq,4*cr1+eq cror 4*cr0+eq,4*cr0+eq,4*cr5+eq + cror 4*cr0+eq,4*cr0+eq,4*cr7+eq bne 2f /* Restore 74xx specific regs */ lwz r4,CS_MSSCR0(r5) |