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| author |   Heiko Stuebner <heiko@sntech.de> | 2022-07-07 01:15:36 +0200 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2022-08-03 17:29:59 -0700 |
| commit | d20ec7529236a2fcdb2d856fc0bd80b409a217fc (patch) | |
| tree | 97c41e3c370f0ec170fb1b3aab81c42e8f1d105e /arch/riscv/Makefile | |
| parent | riscv: Add support for non-coherent devices using zicbom extension (diff) | |
| download | linux-dev-d20ec7529236a2fcdb2d856fc0bd80b409a217fc.tar.xz linux-dev-d20ec7529236a2fcdb2d856fc0bd80b409a217fc.zip | |
riscv: implement cache-management errata for T-Head SoCs
The T-Head C906 and C910 implement a scheme for handling
cache operations different from the generic Zicbom extension.
Add an errata for it next to the generic dma coherency ops.
Reviewed-by: Samuel Holland <samuel@sholland.org>
Tested-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20220706231536.2041855-5-heiko@sntech.de
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/Makefile')
0 files changed, 0 insertions, 0 deletions