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| author |   Palmer Dabbelt <palmer@sifive.com> | 2018-04-02 20:36:33 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2018-04-02 20:36:33 -0700 |
| commit | 2c9046b71bb6ce2386e8847fce92b18aca9127c4 (patch) | |
| tree | 332fc7da3e0d432b5de5113030007f3ef8ae3318 /arch/riscv/configs/defconfig | |
| parent | RISC-V: Add dynamic ftrace support for RISC-V platforms (diff) | |
| parent | riscv/atomic: Strengthen implementations with fences (diff) | |
| download | linux-dev-2c9046b71bb6ce2386e8847fce92b18aca9127c4.tar.xz linux-dev-2c9046b71bb6ce2386e8847fce92b18aca9127c4.zip | |
RISC-V: Assorted memory model fixes
These fixes fall into three categories
* The definiton of __smp_{store_release,load_acquire}, which allow us to
emit a full fence when unnecessary.
* Fixes to avoid relying on the behavior of "*.aqrl" atomics, as those
are specified in the currently released RISC-V memory model draft in
a way that makes them useless for Linux. This might change in the
future, but now the code matches the memory model spec as it's written
so at least we're getting closer to something sane. The actual fix is
to delete the RISC-V specific atomics and drop back to generic
versions that use the new fences from above.
* Cleanups to our atomic macros, which are mostly non-functional
changes.
Unfortunately I haven't given these as thorough of a testing as I
probably should have, but I've poked through the code and they seem
generally OK.
Diffstat (limited to 'arch/riscv/configs/defconfig')
0 files changed, 0 insertions, 0 deletions