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author | Linus Torvalds <torvalds@linux-foundation.org> | 2019-11-27 11:27:59 -0800 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2019-11-27 11:27:59 -0800 |
commit | 6a0e20cd8cddd70ae5c1211ebe102d738ff2069b (patch) | |
tree | 8e1866144a2ef653f941f5a365e3a80fb06b7a68 /arch/riscv/include/asm/pci.h | |
parent | Merge tag 'powerpc-spectre-rsb' of powerpc-CVE-2019-18660.bundle (diff) | |
parent | Merge branch 'next/nommu' into for-next (diff) | |
download | linux-dev-6a0e20cd8cddd70ae5c1211ebe102d738ff2069b.tar.xz linux-dev-6a0e20cd8cddd70ae5c1211ebe102d738ff2069b.zip |
Merge tag 'riscv/for-v5.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V updates from Paul Walmsley:
"New features:
- SECCOMP support
- nommu support
- SBI-less system support
- M-Mode support
- TLB flush optimizations
Other improvements:
- Pass the complete RISC-V ISA string supported by the CPU cores to
userspace, rather than redacting parts of it in the kernel
- Add platform DMA IP block data to the HiFive Unleashed board DT
file
- Add Makefile support for BZ2, LZ4, LZMA, LZO kernel image
compression formats, in line with other architectures
Cleanups:
- Remove unnecessary PTE_PARENT_SIZE macro
- Standardize include guard naming across arch/riscv"
* tag 'riscv/for-v5.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (22 commits)
riscv: provide a flat image loader
riscv: add nommu support
riscv: clear the instruction cache and all registers when booting
riscv: read the hart ID from mhartid on boot
riscv: provide native clint access for M-mode
riscv: dts: add support for PDMA device of HiFive Unleashed Rev A00
riscv: add support for MMIO access to the timer registers
riscv: implement remote sfence.i using IPIs
riscv: cleanup the default power off implementation
riscv: poison SBI calls for M-mode
riscv: don't allow selecting SBI based drivers for M-mode
RISC-V: Add multiple compression image format.
riscv: clean up the macro format in each header file
riscv: Use PMD_SIZE to replace PTE_PARENT_SIZE
riscv: abstract out CSR names for supervisor vs machine mode
riscv: separate MMIO functions into their own header file
riscv: enter WFI in default_power_off() if SBI does not shutdown
RISC-V: Issue a tlb page flush if possible
RISC-V: Issue a local tlbflush if possible.
RISC-V: Do not invoke SBI call if cpumask is empty
...
Diffstat (limited to 'arch/riscv/include/asm/pci.h')
-rw-r--r-- | arch/riscv/include/asm/pci.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/riscv/include/asm/pci.h b/arch/riscv/include/asm/pci.h index 5ac8daa1cc36..1c473a1bd986 100644 --- a/arch/riscv/include/asm/pci.h +++ b/arch/riscv/include/asm/pci.h @@ -3,8 +3,8 @@ * Copyright (C) 2016 SiFive */ -#ifndef __ASM_RISCV_PCI_H -#define __ASM_RISCV_PCI_H +#ifndef _ASM_RISCV_PCI_H +#define _ASM_RISCV_PCI_H #include <linux/types.h> #include <linux/slab.h> @@ -34,4 +34,4 @@ static inline int pci_proc_domain(struct pci_bus *bus) } #endif /* CONFIG_PCI */ -#endif /* __ASM_PCI_H */ +#endif /* _ASM_RISCV_PCI_H */ |