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| author |   Anup Patel <apatel@ventanamicro.com> | 2022-10-02 10:18:37 +0530 |
|---|---|---|
| committer |   Anup Patel <anup@brainfault.org> | 2022-10-02 10:18:37 +0530 |
| commit | 5ff112484f2e63c5cac9f865181ca7ce467d0f89 (patch) | |
| tree | 894c4781a93fc6f3cd82037f324d894bed5b4a34 /arch/riscv/include/asm | |
| parent | RISC-V: Probe Svinval extension form ISA string (diff) | |
| download | linux-dev-5ff112484f2e63c5cac9f865181ca7ce467d0f89.tar.xz linux-dev-5ff112484f2e63c5cac9f865181ca7ce467d0f89.zip | |
RISC-V: KVM: Use Svinval for local TLB maintenance when available
We should prefer HINVAL.GVMA and HINVAL.VVMA instruction for local TLB
maintenance when underlying host supports Svinval extension.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv/include/asm')
| -rw-r--r-- | arch/riscv/include/asm/insn-def.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/insn-def.h index af7b0b55815c..16044affa57c 100644 --- a/arch/riscv/include/asm/insn-def.h +++ b/arch/riscv/include/asm/insn-def.h @@ -114,4 +114,24 @@ __ASM_STR(.error "hlv.d requires 64-bit support") #endif +#define SINVAL_VMA(vaddr, asid) \ + INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(11), \ + __RD(0), RS1(vaddr), RS2(asid)) + +#define SFENCE_W_INVAL() \ + INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(12), \ + __RD(0), __RS1(0), __RS2(0)) + +#define SFENCE_INVAL_IR() \ + INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(12), \ + __RD(0), __RS1(0), __RS2(1)) + +#define HINVAL_VVMA(vaddr, asid) \ + INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(19), \ + __RD(0), RS1(vaddr), RS2(asid)) + +#define HINVAL_GVMA(gaddr, vmid) \ + INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(51), \ + __RD(0), RS1(gaddr), RS2(vmid)) + #endif /* __ASM_INSN_DEF_H */ |