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| author |   Atish Patra <atish.patra@wdc.com> | 2020-03-17 18:11:44 -0700 |
|---|---|---|
| committer |   Palmer Dabbelt <palmerdabbelt@google.com> | 2020-03-31 11:28:30 -0700 |
| commit | f1e58583b9c7ceae7f11646e9edf2561d67f29c9 (patch) | |
| tree | bb55d2b26e3eefea34f6d672cff66b01211d95be /arch/riscv/kernel/setup.c | |
| parent | RISC-V: Add supported for ordered booting method using HSM (diff) | |
| download | linux-dev-f1e58583b9c7ceae7f11646e9edf2561d67f29c9.tar.xz linux-dev-f1e58583b9c7ceae7f11646e9edf2561d67f29c9.zip | |
RISC-V: Support cpu hotplug
This patch enable support for cpu hotplug in RISC-V. It uses SBI HSM
extension to online/offline any hart. As a result, the harts are
returned to firmware once they are offline. If the harts are brought
online afterwards, they re-enter Linux kernel as if a secondary hart
booted for the first time. All booting requirements are honored during
this process.
Tested both on QEMU and HighFive Unleashed board with. Test result follows.
---------------------------------------------------
Offline cpu 2
---------------------------------------------------
$ echo 0 > /sys/devices/system/cpu/cpu2/online
[ 32.828684] CPU2: off
$ cat /proc/cpuinfo
processor : 0
hart : 0
isa : rv64imafdcsu
mmu : sv48
processor : 1
hart : 1
isa : rv64imafdcsu
mmu : sv48
processor : 3
hart : 3
isa : rv64imafdcsu
mmu : sv48
processor : 4
hart : 4
isa : rv64imafdcsu
mmu : sv48
processor : 5
hart : 5
isa : rv64imafdcsu
mmu : sv48
processor : 6
hart : 6
isa : rv64imafdcsu
mmu : sv48
processor : 7
hart : 7
isa : rv64imafdcsu
mmu : sv48
---------------------------------------------------
online cpu 2
---------------------------------------------------
$ echo 1 > /sys/devices/system/cpu/cpu2/online
$ cat /proc/cpuinfo
processor : 0
hart : 0
isa : rv64imafdcsu
mmu : sv48
processor : 1
hart : 1
isa : rv64imafdcsu
mmu : sv48
processor : 2
hart : 2
isa : rv64imafdcsu
mmu : sv48
processor : 3
hart : 3
isa : rv64imafdcsu
mmu : sv48
processor : 4
hart : 4
isa : rv64imafdcsu
mmu : sv48
processor : 5
hart : 5
isa : rv64imafdcsu
mmu : sv48
processor : 6
hart : 6
isa : rv64imafdcsu
mmu : sv48
processor : 7
hart : 7
isa : rv64imafdcsu
mmu : sv48
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv/kernel/setup.c')
| -rw-r--r-- | arch/riscv/kernel/setup.c | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 07f4e7503223..145128a7e560 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -16,12 +16,13 @@ #include <linux/of_platform.h> #include <linux/sched/task.h> #include <linux/swiotlb.h> +#include <linux/smp.h> #include <asm/clint.h> +#include <asm/cpu_ops.h> #include <asm/setup.h> #include <asm/sections.h> #include <asm/pgtable.h> -#include <asm/smp.h> #include <asm/sbi.h> #include <asm/tlbflush.h> #include <asm/thread_info.h> @@ -47,6 +48,7 @@ struct screen_info screen_info = { */ atomic_t hart_lottery __section(.sdata); unsigned long boot_cpu_hartid; +static DEFINE_PER_CPU(struct cpu, cpu_devices); void __init parse_dtb(void) { @@ -94,3 +96,18 @@ void __init setup_arch(char **cmdline_p) riscv_fill_hwcap(); } + +static int __init topology_init(void) +{ + int i; + + for_each_possible_cpu(i) { + struct cpu *cpu = &per_cpu(cpu_devices, i); + + cpu->hotpluggable = cpu_has_hotplug(i); + register_cpu(cpu, i); + } + + return 0; +} +subsys_initcall(topology_init); |