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authorZong Li <zong.li@sifive.com>2020-03-10 00:55:40 +0800
committerPalmer Dabbelt <palmerdabbelt@google.com>2020-03-26 09:24:42 -0700
commit00cb41d5ad3189f52a59f42766918557693f94fa (patch)
treec5a3b7c169462d455d6a96c990b45a7ece963fbd /arch/riscv/kernel/vmlinux.lds.S
parentriscv: move exception table immediately after RO_DATA (diff)
downloadlinux-dev-00cb41d5ad3189f52a59f42766918557693f94fa.tar.xz
linux-dev-00cb41d5ad3189f52a59f42766918557693f94fa.zip
riscv: add alignment for text, rodata and data sections
The kernel mapping will tried to optimize its mapping by using bigger size. In rv64, it tries to use PMD_SIZE, and tryies to use PGDIR_SIZE in rv32. To ensure that the start address of these sections could fit the mapping entry size, make them align to the biggest alignment. Define a macro SECTION_ALIGN because the HPAGE_SIZE or PMD_SIZE, etc., are invisible in linker script. This patch is prepared for STRICT_KERNEL_RWX support. Signed-off-by: Zong Li <zong.li@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'arch/riscv/kernel/vmlinux.lds.S')
-rw-r--r--arch/riscv/kernel/vmlinux.lds.S5
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/riscv/kernel/vmlinux.lds.S b/arch/riscv/kernel/vmlinux.lds.S
index 9e8adca9b20f..4ad3c8eb241d 100644
--- a/arch/riscv/kernel/vmlinux.lds.S
+++ b/arch/riscv/kernel/vmlinux.lds.S
@@ -9,6 +9,7 @@
#include <asm/page.h>
#include <asm/cache.h>
#include <asm/thread_info.h>
+#include <asm/set_memory.h>
OUTPUT_ARCH(riscv)
ENTRY(_start)
@@ -36,6 +37,7 @@ SECTIONS
PERCPU_SECTION(L1_CACHE_BYTES)
__init_end = .;
+ . = ALIGN(SECTION_ALIGN);
.text : {
_text = .;
_stext = .;
@@ -53,13 +55,14 @@ SECTIONS
/* Start of data section */
_sdata = .;
- RO_DATA(L1_CACHE_BYTES)
+ RO_DATA(SECTION_ALIGN)
.srodata : {
*(.srodata*)
}
EXCEPTION_TABLE(0x10)
+ . = ALIGN(SECTION_ALIGN);
_data = .;
RW_DATA(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)