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authorPaul Mundt <lethal@linux-sh.org>2010-01-20 15:23:54 +0900
committerPaul Mundt <lethal@linux-sh.org>2010-01-20 15:23:54 +0900
commit5f240718b475dcddee86b138b624f24c681dbb29 (patch)
tree22ef5b5cc9e515496a1e4cb987ae9d5d255ca31d /arch/sh/boards/mach-sdk7786/irq.c
parentsh: mach-sdk7786: FPGA updates. (diff)
downloadlinux-dev-5f240718b475dcddee86b138b624f24c681dbb29.tar.xz
linux-dev-5f240718b475dcddee86b138b624f24c681dbb29.zip
sh: mach-sdk7786: Split out FPGA IRQ controller setup.
This moves out the FPGA IRQ controller setup code to its own file, in preparation for switching off of IRL mode and having it provide its own irq_chip. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/boards/mach-sdk7786/irq.c')
-rw-r--r--arch/sh/boards/mach-sdk7786/irq.c48
1 files changed, 48 insertions, 0 deletions
diff --git a/arch/sh/boards/mach-sdk7786/irq.c b/arch/sh/boards/mach-sdk7786/irq.c
new file mode 100644
index 000000000000..46943a0da5b7
--- /dev/null
+++ b/arch/sh/boards/mach-sdk7786/irq.c
@@ -0,0 +1,48 @@
+/*
+ * SDK7786 FPGA IRQ Controller Support.
+ *
+ * Copyright (C) 2010 Matt Fleming
+ * Copyright (C) 2010 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/irq.h>
+#include <mach/fpga.h>
+#include <mach/irq.h>
+
+enum {
+ ATA_IRQ_BIT = 1,
+ SPI_BUSY_BIT = 2,
+ LIRQ5_BIT = 3,
+ LIRQ6_BIT = 4,
+ LIRQ7_BIT = 5,
+ LIRQ8_BIT = 6,
+ KEY_IRQ_BIT = 7,
+ PEN_IRQ_BIT = 8,
+ ETH_IRQ_BIT = 9,
+ RTC_ALARM_BIT = 10,
+ CRYSTAL_FAIL_BIT = 12,
+ ETH_PME_BIT = 14,
+};
+
+void __init sdk7786_init_irq(void)
+{
+ unsigned int tmp;
+
+ /* Enable priority encoding for all IRLs */
+ fpga_write_reg(fpga_read_reg(INTMSR) | 0x0303, INTMSR);
+
+ /* Clear FPGA interrupt status registers */
+ fpga_write_reg(0x0000, INTASR);
+ fpga_write_reg(0x0000, INTBSR);
+
+ /* Unmask FPGA interrupts */
+ tmp = fpga_read_reg(INTAMR);
+ tmp &= ~(1 << ETH_IRQ_BIT);
+ fpga_write_reg(tmp, INTAMR);
+
+ plat_irq_setup_pins(IRQ_MODE_IRL7654_MASK);
+ plat_irq_setup_pins(IRQ_MODE_IRL3210_MASK);
+}