diff options
| author |   Paul Mundt <lethal@linux-sh.org> | 2012-05-19 20:38:50 +0900 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2012-05-19 20:38:50 +0900 |
| commit | 7f47c7189b3e8f19a589f77a3ad169d7b691b582 (patch) | |
| tree | c7a92d4c0e01c729ab93c83a616cf90b004e514d /arch/sh/include/cpu-sh4a | |
| parent | sh: Kill off MAX_DMA_ADDRESS leftovers. (diff) | |
| download | linux-dev-7f47c7189b3e8f19a589f77a3ad169d7b691b582.tar.xz linux-dev-7f47c7189b3e8f19a589f77a3ad169d7b691b582.zip | |
sh: dma: More legacy cpu dma chainsawing.
Attempt to "tidy" up some of the multi IRQ handling and base + IRQ
management. This should keep it limping along without too much hassle,
and no new parts should ever be enabling or using this API anyways.
It doesn't get any closer to lipstick on a pig as this.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include/cpu-sh4a')
| -rw-r--r-- | arch/sh/include/cpu-sh4a/cpu/dma.h | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/arch/sh/include/cpu-sh4a/cpu/dma.h b/arch/sh/include/cpu-sh4a/cpu/dma.h index c276313104c7..89afb650ce25 100644 --- a/arch/sh/include/cpu-sh4a/cpu/dma.h +++ b/arch/sh/include/cpu-sh4a/cpu/dma.h @@ -9,20 +9,17 @@ #define DMTE4_IRQ evt2irq(0xb80) #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/ #define SH_DMAC_BASE0 0xFE008020 -#define SH_DMARS_BASE0 0xFE009000 #elif defined(CONFIG_CPU_SUBTYPE_SH7722) #define DMTE0_IRQ evt2irq(0x800) #define DMTE4_IRQ evt2irq(0xb80) #define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/ #define SH_DMAC_BASE0 0xFE008020 -#define SH_DMARS_BASE0 0xFE009000 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ defined(CONFIG_CPU_SUBTYPE_SH7764) #define DMTE0_IRQ evt2irq(0x640) #define DMTE4_IRQ evt2irq(0x780) #define DMAE0_IRQ evt2irq(0x6c0) #define SH_DMAC_BASE0 0xFF608020 -#define SH_DMARS_BASE0 0xFF609000 #elif defined(CONFIG_CPU_SUBTYPE_SH7723) #define DMTE0_IRQ evt2irq(0x800) /* DMAC0A*/ #define DMTE4_IRQ evt2irq(0xb80) /* DMAC0B */ @@ -35,7 +32,6 @@ #define DMAE1_IRQ evt2irq(0xb40) /* DMA Error IRQ*/ #define SH_DMAC_BASE0 0xFE008020 #define SH_DMAC_BASE1 0xFDC08020 -#define SH_DMARS_BASE0 0xFDC09000 #elif defined(CONFIG_CPU_SUBTYPE_SH7724) #define DMTE0_IRQ evt2irq(0x800) /* DMAC0A*/ #define DMTE4_IRQ evt2irq(0xb80) /* DMAC0B */ @@ -48,8 +44,6 @@ #define DMAE1_IRQ evt2irq(0xb40) /* DMA Error IRQ*/ #define SH_DMAC_BASE0 0xFE008020 #define SH_DMAC_BASE1 0xFDC08020 -#define SH_DMARS_BASE0 0xFE009000 -#define SH_DMARS_BASE1 0xFDC09000 #elif defined(CONFIG_CPU_SUBTYPE_SH7780) #define DMTE0_IRQ evt2irq(0x640) #define DMTE4_IRQ evt2irq(0x780) @@ -61,7 +55,6 @@ #define DMAE0_IRQ evt2irq(0x6c0) /* DMA Error IRQ */ #define SH_DMAC_BASE0 0xFC808020 #define SH_DMAC_BASE1 0xFC818020 -#define SH_DMARS_BASE0 0xFC809000 #else /* SH7785 */ #define DMTE0_IRQ evt2irq(0x620) #define DMTE4_IRQ evt2irq(0x6a0) @@ -74,7 +67,6 @@ #define DMAE1_IRQ evt2irq(0x940) /* DMA Error IRQ1 */ #define SH_DMAC_BASE0 0xFC808020 #define SH_DMAC_BASE1 0xFCC08020 -#define SH_DMARS_BASE0 0xFC809000 #endif #endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */ |