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authorPaul Mundt <lethal@linux-sh.org>2007-05-08 15:31:48 +0900
committerPaul Mundt <lethal@hera.kernel.org>2007-05-09 01:35:01 +0000
commit53f983a90d7908bcece51f86180c7c9b575a1e4d (patch)
treeda5914e6f18e8dd55563697de7339af2d99d9c18 /arch/sh/kernel/cpu/sh4
parentsh: Support for SH-2A 32-bit opcodes. (diff)
downloadlinux-dev-53f983a90d7908bcece51f86180c7c9b575a1e4d.tar.xz
linux-dev-53f983a90d7908bcece51f86180c7c9b575a1e4d.zip
sh: Fix PC adjustments for varying opcode length.
There are a few different cases for figuring out how to size the instruction. We read in the instruction located at regs->pc - 4 when rewinding the opcode to figure out if there's a 32-bit opcode before the faulting instruction, with a default of a - 2 adjustment on a mismatch. In practice this works for the cases where pc - 4 is just another 16-bit opcode, or we happen to have a 32-bit and a 16-bit immediately preceeding the pc value. In the cases where we aren't rewinding, this is much less ugly.. We also don't bother fixing up the places where we're explicitly dealing with 16-bit instructions, since this might lead to confusion regarding the encoding size possibilities on other CPU variants. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/sh4')
-rw-r--r--arch/sh/kernel/cpu/sh4/fpu.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/sh/kernel/cpu/sh4/fpu.c b/arch/sh/kernel/cpu/sh4/fpu.c
index 7624677f6628..d61dd599169f 100644
--- a/arch/sh/kernel/cpu/sh4/fpu.c
+++ b/arch/sh/kernel/cpu/sh4/fpu.c
@@ -16,6 +16,7 @@
#include <linux/sched.h>
#include <linux/signal.h>
#include <asm/processor.h>
+#include <asm/system.h>
#include <asm/io.h>
/* The PR (precision) bit in the FP Status Register must be clear when
@@ -265,7 +266,7 @@ ieee_fpe_handler (struct pt_regs *regs)
nextpc = regs->pr;
finsn = *(unsigned short *) (regs->pc + 2);
} else {
- nextpc = regs->pc + 2;
+ nextpc = regs->pc + instruction_size(insn);
finsn = insn;
}