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authorPaul Mundt <lethal@linux-sh.org>2006-09-27 18:28:34 +0900
committerPaul Mundt <lethal@linux-sh.org>2006-09-27 18:28:34 +0900
commitd15f456043175bdf3464514b92a825b88d0546ae (patch)
treeb98ee188453dd5d79ca433c63993bad21c9ca38b /arch/sh/kernel/cpu/sh4
parentsh: Support for L2 cache on newer SH-4A CPUs. (diff)
downloadlinux-dev-d15f456043175bdf3464514b92a825b88d0546ae.tar.xz
linux-dev-d15f456043175bdf3464514b92a825b88d0546ae.zip
sh: More intelligent entry_mask/way_size calculation.
Figure out the cache desc entry_mask at runtime, and remove hard-coded assumption about the cacheline size. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/sh4')
-rw-r--r--arch/sh/kernel/cpu/sh4/probe.c20
1 files changed, 13 insertions, 7 deletions
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index bee00cac0b16..c294de1e14a3 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -38,7 +38,6 @@ int __init detect_cpu_and_cache_system(void)
*/
cpu_data->icache.way_incr = (1 << 13);
cpu_data->icache.entry_shift = 5;
- cpu_data->icache.entry_mask = 0x1fe0;
cpu_data->icache.sets = 256;
cpu_data->icache.ways = 1;
cpu_data->icache.linesz = L1_CACHE_BYTES;
@@ -48,7 +47,6 @@ int __init detect_cpu_and_cache_system(void)
*/
cpu_data->dcache.way_incr = (1 << 14);
cpu_data->dcache.entry_shift = 5;
- cpu_data->dcache.entry_mask = 0x3fe0;
cpu_data->dcache.sets = 512;
cpu_data->dcache.ways = 1;
cpu_data->dcache.linesz = L1_CACHE_BYTES;
@@ -183,21 +181,26 @@ int __init detect_cpu_and_cache_system(void)
size = sizes[(cvr >> 20) & 0xf];
cpu_data->icache.way_incr = (size >> 1);
cpu_data->icache.sets = (size >> 6);
- cpu_data->icache.entry_mask =
- (cpu_data->icache.way_incr - (1 << 5));
+
}
+ /* Setup the rest of the I-cache info */
+ cpu_data->icache.entry_mask = cpu_data->icache.way_incr -
+ cpu_data->icache.linesz;
+
cpu_data->icache.way_size = cpu_data->icache.sets *
cpu_data->icache.linesz;
+ /* And the rest of the D-cache */
if (cpu_data->dcache.ways > 1) {
size = sizes[(cvr >> 16) & 0xf];
cpu_data->dcache.way_incr = (size >> 1);
cpu_data->dcache.sets = (size >> 6);
- cpu_data->dcache.entry_mask =
- (cpu_data->dcache.way_incr - (1 << 5));
}
+ cpu_data->dcache.entry_mask = cpu_data->dcache.way_incr -
+ cpu_data->dcache.linesz;
+
cpu_data->dcache.way_size = cpu_data->dcache.sets *
cpu_data->dcache.linesz;
@@ -219,11 +222,14 @@ int __init detect_cpu_and_cache_system(void)
cpu_data->scache.way_incr = (1 << 16);
cpu_data->scache.entry_shift = 5;
- cpu_data->scache.entry_mask = 0xffe0;
cpu_data->scache.ways = 4;
cpu_data->scache.linesz = L1_CACHE_BYTES;
+ cpu_data->scache.entry_mask =
+ (cpu_data->scache.way_incr - cpu_data->scache.linesz);
cpu_data->scache.sets = size /
(cpu_data->scache.linesz * cpu_data->scache.ways);
+ cpu_data->scache.way_size =
+ (cpu_data->scache.sets * cpu_data->scache.linesz);
}
return 0;