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author | James Morris <jmorris@namei.org> | 2010-01-18 09:56:22 +1100 |
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committer | James Morris <jmorris@namei.org> | 2010-01-18 09:56:22 +1100 |
commit | 2457552d1e6f3183cd93f81c49a8da5fe8bb0e42 (patch) | |
tree | 7ca46caa910012d75617700e4083b3657053cb31 /arch/sh/mm/Kconfig | |
parent | selinux: change the handling of unknown classes (diff) | |
parent | page allocator: update NR_FREE_PAGES only when necessary (diff) | |
download | linux-dev-2457552d1e6f3183cd93f81c49a8da5fe8bb0e42.tar.xz linux-dev-2457552d1e6f3183cd93f81c49a8da5fe8bb0e42.zip |
Merge branch 'master' into next
Diffstat (limited to 'arch/sh/mm/Kconfig')
-rw-r--r-- | arch/sh/mm/Kconfig | 20 |
1 files changed, 12 insertions, 8 deletions
diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig index 7f7b52f9beba..986a71b88ca3 100644 --- a/arch/sh/mm/Kconfig +++ b/arch/sh/mm/Kconfig @@ -82,9 +82,7 @@ config 32BIT config PMB_ENABLE bool "Support 32-bit physical addressing through PMB" - depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7757 || CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785) - select 32BIT - default y + depends on MMU && EXPERIMENTAL && CPU_SH4A && !CPU_SH4AL_DSP help If you say Y here, physical addressing will be extended to 32-bits through the SH-4A PMB. If this is not set, legacy @@ -97,8 +95,7 @@ choice config PMB bool "PMB" - depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7757 || CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785) - select 32BIT + depends on MMU && EXPERIMENTAL && CPU_SH4A && !CPU_SH4AL_DSP help If you say Y here, physical addressing will be extended to 32-bits through the SH-4A PMB. If this is not set, legacy @@ -106,9 +103,7 @@ config PMB config PMB_FIXED bool "fixed PMB" - depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7757 || \ - CPU_SUBTYPE_SH7780 || \ - CPU_SUBTYPE_SH7785) + depends on MMU && EXPERIMENTAL && CPU_SH4A && !CPU_SH4AL_DSP select 32BIT help If this option is enabled, fixed PMB mappings are inherited @@ -258,6 +253,15 @@ endchoice source "mm/Kconfig" +config SCHED_MC + bool "Multi-core scheduler support" + depends on SMP + default y + help + Multi-core scheduler support improves the CPU scheduler's decision + making when dealing with multi-core CPU chips at a cost of slightly + increased overhead in some places. If unsure say N here. + endmenu menu "Cache configuration" |