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authorbob picco <bpicco@meloft.net>2014-09-16 10:09:06 -0400
committerDavid S. Miller <davem@davemloft.net>2014-09-16 18:26:40 -0700
commit05aa1651e8b9ca078b1808a2fe7b50703353ec02 (patch)
tree9a3cb98b69a4f1960c627586975043bcb364c82e /arch/sparc/include/asm/ldc.h
parentsparc64: mem boot option correction (diff)
downloadlinux-dev-05aa1651e8b9ca078b1808a2fe7b50703353ec02.tar.xz
linux-dev-05aa1651e8b9ca078b1808a2fe7b50703353ec02.zip
sparc64: T5 PMU
The T5 (niagara5) has different PCR related HV fast trap values and a new HV API Group. This patch utilizes these and shares when possible with niagara4. We use the same sparc_pmu niagara4_pmu. Should there be new effort to obtain the MCU perf statistics then this would have to be changed. Cc: sparclinux@vger.kernel.org Signed-off-by: Bob Picco <bob.picco@oracle.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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