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| author |   David S. Miller <davem@davemloft.net> | 2011-09-11 10:42:20 -0700 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2011-09-16 14:21:33 -0700 |
| commit | 08cefa9fa7e5b3ddaefb8b7bfa408d148429c08d (patch) | |
| tree | 07a33d960d2ce5d72733dd21cf8d179fd06d145a /arch/sparc/include | |
| parent | sparc64: Only Panther cheetah+ chips have POPC. (diff) | |
| download | linux-dev-08cefa9fa7e5b3ddaefb8b7bfa408d148429c08d.tar.xz linux-dev-08cefa9fa7e5b3ddaefb8b7bfa408d148429c08d.zip | |
sparc64: Future proof Niagara cpu detection.
Recognize T4 and T5 chips. Treating them both as "T2 plus other
stuff" should be extremely safe and make sure distributions will work
when those chips actually ship to customers.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc/include')
| -rw-r--r-- | arch/sparc/include/asm/spitfire.h | 2 | ||||
| -rw-r--r-- | arch/sparc/include/asm/xor_64.h | 4 |
2 files changed, 5 insertions, 1 deletions
diff --git a/arch/sparc/include/asm/spitfire.h b/arch/sparc/include/asm/spitfire.h index 55a17c6efeb8..d06a26601753 100644 --- a/arch/sparc/include/asm/spitfire.h +++ b/arch/sparc/include/asm/spitfire.h @@ -43,6 +43,8 @@ #define SUN4V_CHIP_NIAGARA1 0x01 #define SUN4V_CHIP_NIAGARA2 0x02 #define SUN4V_CHIP_NIAGARA3 0x03 +#define SUN4V_CHIP_NIAGARA4 0x04 +#define SUN4V_CHIP_NIAGARA5 0x05 #define SUN4V_CHIP_UNKNOWN 0xff #ifndef __ASSEMBLY__ diff --git a/arch/sparc/include/asm/xor_64.h b/arch/sparc/include/asm/xor_64.h index 9ed6ff679ab7..ee8edc68423e 100644 --- a/arch/sparc/include/asm/xor_64.h +++ b/arch/sparc/include/asm/xor_64.h @@ -66,6 +66,8 @@ static struct xor_block_template xor_block_niagara = { ((tlb_type == hypervisor && \ (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || \ sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || \ - sun4v_chip_type == SUN4V_CHIP_NIAGARA3)) ? \ + sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || \ + sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || \ + sun4v_chip_type == SUN4V_CHIP_NIAGARA5)) ? \ &xor_block_niagara : \ &xor_block_VIS) |