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author | 2020-05-13 15:32:00 -0700 | |
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committer | 2020-05-13 15:32:00 -0700 | |
commit | a012c1e866a65699c806ae4a35d267de29fe85e7 (patch) | |
tree | 78c7e162e943477819899cb9c2d3a64f994bd5c9 /arch/sparc/kernel | |
parent | Merge tag 'trace-v5.7-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace (diff) | |
parent | sparc32: mm: Reduce allocation size for PMD and PTE tables (diff) | |
download | linux-dev-a012c1e866a65699c806ae4a35d267de29fe85e7.tar.xz linux-dev-a012c1e866a65699c806ae4a35d267de29fe85e7.zip |
Merge branch 'Rework-sparc32-page-table-layout'
Will Deacon says:
====================
Rework sparc32 page-table layout
This is a reposting of the patch series I sent previously to rework the
sparc32 page-table layout so that 'pmd_t' can be used safely with
READ_ONCE():
https://lore.kernel.org/lkml/20200324104005.11279-1-will@kernel.org
This is blocking the READ_ONCE() rework, which in turn allows us to
bump the minimum GCC version for building the kernel up to 4.8.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc/kernel')
-rw-r--r-- | arch/sparc/kernel/head_32.S | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/sparc/kernel/head_32.S b/arch/sparc/kernel/head_32.S index e55f2c075165..be30c8d4cc73 100644 --- a/arch/sparc/kernel/head_32.S +++ b/arch/sparc/kernel/head_32.S @@ -24,7 +24,7 @@ #include <asm/winmacro.h> #include <asm/thread_info.h> /* TI_UWINMASK */ #include <asm/errno.h> -#include <asm/pgtsrmmu.h> /* SRMMU_PGDIR_SHIFT */ +#include <asm/pgtable.h> /* PGDIR_SHIFT */ #include <asm/export.h> .data @@ -273,7 +273,7 @@ not_a_sun4: lda [%o1] ASI_M_BYPASS, %o2 ! This is the 0x0 16MB pgd /* Calculate to KERNBASE entry. */ - add %o1, KERNBASE >> (SRMMU_PGDIR_SHIFT - 2), %o3 + add %o1, KERNBASE >> (PGDIR_SHIFT - 2), %o3 /* Poke the entry into the calculated address. */ sta %o2, [%o3] ASI_M_BYPASS @@ -317,7 +317,7 @@ srmmu_not_viking: sll %g1, 0x8, %g1 ! make phys addr for l1 tbl lda [%g1] ASI_M_BYPASS, %g2 ! get level1 entry for 0x0 - add %g1, KERNBASE >> (SRMMU_PGDIR_SHIFT - 2), %g3 + add %g1, KERNBASE >> (PGDIR_SHIFT - 2), %g3 sta %g2, [%g3] ASI_M_BYPASS ! place at KERNBASE entry b go_to_highmem nop ! wheee.... @@ -341,7 +341,7 @@ leon_remap: sll %g1, 0x8, %g1 ! make phys addr for l1 tbl lda [%g1] ASI_M_BYPASS, %g2 ! get level1 entry for 0x0 - add %g1, KERNBASE >> (SRMMU_PGDIR_SHIFT - 2), %g3 + add %g1, KERNBASE >> (PGDIR_SHIFT - 2), %g3 sta %g2, [%g3] ASI_M_BYPASS ! place at KERNBASE entry b go_to_highmem nop ! wheee.... |