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| author |   David S. Miller <davem@davemloft.net> | 2009-09-10 07:13:26 -0700 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2009-09-10 07:13:26 -0700 |
| commit | 660d13765f342ecb6e774fcbc35b64beb0a069da (patch) | |
| tree | 95987ea10feb7546ec6539742c60a89a129a2e21 /arch/sparc | |
| parent | sparc64: Provide a way to specify a perf counter overflow IRQ enable bit. (diff) | |
| download | linux-dev-660d13765f342ecb6e774fcbc35b64beb0a069da.tar.xz linux-dev-660d13765f342ecb6e774fcbc35b64beb0a069da.zip | |
sparc64: Perf counter 'nop' event is not constant.
On Niagara-2, for example, it's going to be different. So make
it something specified in sparc_pmu.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc')
| -rw-r--r-- | arch/sparc/kernel/perf_counter.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/sparc/kernel/perf_counter.c b/arch/sparc/kernel/perf_counter.c index 0cd5487b3413..f3b8ccca3c92 100644 --- a/arch/sparc/kernel/perf_counter.c +++ b/arch/sparc/kernel/perf_counter.c @@ -52,9 +52,6 @@ #define PIC_UPPER_INDEX 0 #define PIC_LOWER_INDEX 1 -#define PIC_UPPER_NOP 0x1c -#define PIC_LOWER_NOP 0x14 - struct cpu_hw_counters { struct perf_counter *counters[MAX_HWCOUNTERS]; unsigned long used_mask[BITS_TO_LONGS(MAX_HWCOUNTERS)]; @@ -79,6 +76,8 @@ struct sparc_pmu { int event_mask; int hv_bit; int irq_bit; + int upper_nop; + int lower_nop; }; static const struct perf_event_map ultra3i_perfmon_event_map[] = { @@ -99,6 +98,8 @@ static const struct sparc_pmu ultra3i_pmu = { .upper_shift = 11, .lower_shift = 4, .event_mask = 0x3f, + .upper_nop = 0x1c, + .lower_nop = 0x14, }; static const struct sparc_pmu *sparc_pmu __read_mostly; @@ -120,7 +121,8 @@ static u64 mask_for_index(int idx) static u64 nop_for_index(int idx) { return event_encoding(idx == PIC_UPPER_INDEX ? - PIC_UPPER_NOP : PIC_LOWER_NOP, idx); + sparc_pmu->upper_nop : + sparc_pmu->lower_nop, idx); } static inline void sparc_pmu_enable_counter(struct hw_perf_counter *hwc, |