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| author |   Vineet Gupta <vgupta@synopsys.com> | 2017-08-22 14:37:22 -0700 |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2017-09-01 11:26:26 -0700 |
| commit | 0fa400cb8a90753044bbcb5810fa1a59d96d5ea1 (patch) | |
| tree | 76080e940d4b0fdde189ea918e80295a10f6e8c5 /arch/tile | |
| parent | ARC: [plat-axs103] use clk driver #2: Add core pll node to DT to manage cpu clk (diff) | |
| download | linux-dev-0fa400cb8a90753044bbcb5810fa1a59d96d5ea1.tar.xz linux-dev-0fa400cb8a90753044bbcb5810fa1a59d96d5ea1.zip | |
ARC: [plat-axs103] refactor the DT fudging code
with clk frequency setting code gone by prev commits, we can elide the
unconditonal DT parsing to the specific case of quad core config where
we possibly need to fudge the DT value.
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/tile')
0 files changed, 0 insertions, 0 deletions