path: root/arch/x86/events/intel/core.c
diff options
authorAdrian Hunter <adrian.hunter@intel.com>2021-09-07 19:39:01 +0300
committerPeter Zijlstra <peterz@infradead.org>2021-10-15 11:25:31 +0200
commit8b8ff8cc3b8155c18162e8b1f70e1230db176862 (patch)
tree7fa6284dbe477808c4a93170cfb6ea7ac5463980 /arch/x86/events/intel/core.c
parentperf/x86: Add compiler barrier after updating BTS (diff)
perf/x86: Add new event for AUX output counter index
PEBS-via-PT records contain a mask of applicable counters. To identify which event belongs to which counter, a side-band event is needed. Until now, there has been no side-band event, and consequently users were limited to using a single event. Add such a side-band event. Note the event is optimised to output only when the counter index changes for an event. That works only so long as all PEBS-via-PT events are scheduled together, which they are for a recording session because they are in a single group. Also no attribute bit is used to select the new event, so a new kernel is not compatible with older perf tools. The assumption being that PEBS-via-PT is sufficiently esoteric that users will not be troubled by this. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20210907163903.11820-2-adrian.hunter@intel.com
Diffstat (limited to 'arch/x86/events/intel/core.c')
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 7011e87be6d0..a555e7c2dce9 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -2402,6 +2402,12 @@ static void intel_pmu_disable_event(struct perf_event *event)
+static void intel_pmu_assign_event(struct perf_event *event, int idx)
+ if (is_pebs_pt(event))
+ perf_report_aux_output_id(event, idx);
static void intel_pmu_del_event(struct perf_event *event)
if (needs_branch_stack(event))
@@ -4494,8 +4500,16 @@ static int intel_pmu_check_period(struct perf_event *event, u64 value)
return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0;
+static void intel_aux_output_init(void)
+ /* Refer also intel_pmu_aux_output_match() */
+ if (x86_pmu.intel_cap.pebs_output_pt_available)
+ x86_pmu.assign = intel_pmu_assign_event;
static int intel_pmu_aux_output_match(struct perf_event *event)
+ /* intel_pmu_assign_event() is needed, refer intel_aux_output_init() */
if (!x86_pmu.intel_cap.pebs_output_pt_available)
return 0;
@@ -6301,6 +6315,8 @@ __init int intel_pmu_init(void)
if (is_hybrid())
+ intel_aux_output_init();
return 0;