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| author |   Sean Paul <seanpaul@chromium.org> | 2017-05-18 09:24:30 -0400 |
|---|---|---|
| committer | Sean Paul <seanpaul@chromium.org> | 2017-05-18 09:24:30 -0400 |
| commit | 6b7781b42dc9bc9bcd1523b6c24b876cdda0bef3 (patch) | |
| tree | ee55c67e4ea30b9eb44f301ba0bde2e631a26162 /arch/x86/include/asm/intel_pmc_ipc.h | |
| parent | drm/sti:fix spelling mistake: "compoment" -> "component" (diff) | |
| parent | Merge tag 'drm-misc-next-2017-05-16' of git://anongit.freedesktop.org/git/drm-misc into drm-next (diff) | |
| download | linux-dev-6b7781b42dc9bc9bcd1523b6c24b876cdda0bef3.tar.xz linux-dev-6b7781b42dc9bc9bcd1523b6c24b876cdda0bef3.zip | |
Merge remote-tracking branch 'airlied/drm-next' into drm-misc-next
Picking up drm-next @ 4.12-rc1 in order to apply Michal Hocko's vmalloc patch set
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Diffstat (limited to 'arch/x86/include/asm/intel_pmc_ipc.h')
| -rw-r--r-- | arch/x86/include/asm/intel_pmc_ipc.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/x86/include/asm/intel_pmc_ipc.h b/arch/x86/include/asm/intel_pmc_ipc.h index 4291b6a5ddf7..fac89eb78a6b 100644 --- a/arch/x86/include/asm/intel_pmc_ipc.h +++ b/arch/x86/include/asm/intel_pmc_ipc.h @@ -23,6 +23,11 @@ #define IPC_ERR_EMSECURITY 6 #define IPC_ERR_UNSIGNEDKERNEL 7 +/* GCR reg offsets from gcr base*/ +#define PMC_GCR_PMC_CFG_REG 0x08 +#define PMC_GCR_TELEM_DEEP_S0IX_REG 0x78 +#define PMC_GCR_TELEM_SHLW_S0IX_REG 0x80 + #if IS_ENABLED(CONFIG_INTEL_PMC_IPC) int intel_pmc_ipc_simple_command(int cmd, int sub); @@ -31,6 +36,9 @@ int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen, int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen, u32 *out, u32 outlen); int intel_pmc_s0ix_counter_read(u64 *data); +int intel_pmc_gcr_read(u32 offset, u32 *data); +int intel_pmc_gcr_write(u32 offset, u32 data); +int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val); #else @@ -56,6 +64,21 @@ static inline int intel_pmc_s0ix_counter_read(u64 *data) return -EINVAL; } +static inline int intel_pmc_gcr_read(u32 offset, u32 *data) +{ + return -EINVAL; +} + +static inline int intel_pmc_gcr_write(u32 offset, u32 data) +{ + return -EINVAL; +} + +static inline int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val) +{ + return -EINVAL; +} + #endif /*CONFIG_INTEL_PMC_IPC*/ #endif |